The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and handhelds such as the Compaq IPAQ. ARM-based PCs are no longer manufactured, but legacy ARM-based PC hardware remains popular in Europe. There is an ARM Linux project with a web page at <http://www.arm.linux.org.uk/>.
DMA mapping framework by default aligns all buffers to the smallest PAGE_SIZE order which is greater than or equal to the requested buffer size. This works well for buffers up to a few hundreds kilobytes, but for larger buffers it just a waste of address space. Drivers which has relatively small addressing window (like 64Mib) might run out of virtual space with just a few allocations. With this parameter you can specify the maximum PAGE_SIZE order for DMA IOMMU buffers. Larger buffers will be aligned only to this specified order. The order is expressed as a power of two multiplied by the PAGE_SIZE.
Patch phys-to-virt and virt-to-phys translation functions at boot and module load time according to the position of the kernel in system memory. This can only be used with non-XIP MMU kernels where the base of physical memory is at a 2 MiB boundary. Only disable this option if you know that you do not require this feature (eg, building a kernel for a single machine) and you need to shrink the kernel to the minimal size.
Select this when mach/io.h is required to provide special definitions for this platform. The need for mach/io.h should be avoided when possible.
Select this when mach/memory.h is required to provide special definitions for this platform. The need for mach/memory.h should be avoided when possible.
Please provide the physical address corresponding to the location of main memory in your system.
Select if you want MMU-based virtualised addressing space support by paged memory management. If unsure, say 'Y'.
This enables support for the Cirrus EP93xx series of CPUs.
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
Support for Intel's 80219 and IOP32X (XScale) family of processors.
Support for Intel's IXP4XX (XScale) family of processors.
Support for the Marvell Dove SoC 88AP510
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive.
Support for StrongARM 11x0 based boards.
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives).
Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 high performance microcontrollers.
Support for Cortex-M Prototyping System (or V2M-MPS2) which comes with a range of available cores like Cortex-M3/M4/M7. Please, note that depends which Application Note is used memory map for the platform may vary, so adjustment of RAM base might be needed.
Enable support for iWMMXt context switching at run time if running on a CPU that supports it.
When coming out of either a Wait for Interrupt (WFI) or a Wait for Event (WFE) IDLE states, a specific timing sensitivity exists between the retiring WFI/WFE instructions and the newly issued subsequent instructions. This sensitivity can result in a CPU hang scenario. Workaround: The software must insert either a Data Synchronization Barrier (DSB) or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction
Executing a SWP instruction to read-only memory does not set bit 11 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to treat the access as a read, preventing a COW from occurring and causing the faulting task to livelock.
Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround.
This option enables the workaround for the 430973 Cortex-A8 r1p* erratum. If a code sequence containing an ARM/Thumb interworking branch is replaced with another code sequence at the same virtual address, whether due to self-modifying code or virtual to physical address re-mapping, Cortex-A8 does not recover from the stale interworking branch prediction. This results in Cortex-A8 executing the new code sequence in the incorrect ARM or Thumb state. The workaround enables the BTB/BTAC operations by setting ACTLR.IBE and also flushes the branch target cache at every context switch. Note that setting specific bits in the ACTLR register may not be available in non-secure mode.
This option enables the workaround for the 458693 Cortex-A8 (r2p0) erratum. For very specific sequences of memory operations, it is possible for a hazard condition intended for a cache line to instead be incorrectly associated with a different cache line. This false hazard might then cause a processor deadlock. The workaround enables the L1 caching of the NEON accesses and disables the PLD instruction in the ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode.
This option enables the workaround for the 460075 Cortex-A8 (r2p0) erratum. Any asynchronous access to the L2 cache may encounter a situation in which recent store transactions to the L2 cache are lost and overwritten with stale memory contents from external memory. The workaround disables the write-allocate mode for the L2 cache via the ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode.
This option enables the workaround for the 742230 Cortex-A9 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction between two write operations may not ensure the correct visibility ordering of the two writes. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which causes the DMB instruction to behave as a DSB, ensuring the correct behaviour of the two writes.
This option enables the workaround for the 742231 Cortex-A9 (r2p0..r2p2) erratum. Under certain conditions, specific to the Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, accessing some data located in the same cache line, may get corrupted data due to bad handling of the address hazard when the line gets replaced from one of the CPUs at the same time as another CPU is accessing it. This workaround sets specific bits in the diagnostic register of the Cortex-A9 which reduces the linefill issuing capabilities of the processor.
This option enables the workaround for the 643719 Cortex-A9 (prior to r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR register returns zero when it should return one. The workaround corrects this value, ensuring cache maintenance operations which use it behave as intended and avoiding data corruption.
This option enables the workaround for the 720789 Cortex-A9 (prior to r2p0) erratum. A faulty ASID can be sent to the other CPUs for the broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. As a consequence of this erratum, some TLB entries which should be invalidated are not, resulting in an incoherency in the system page tables. The workaround changes the TLB flushing routines to invalidate entries regardless of the ASID.
This option enables the workaround for the 743622 Cortex-A9 (r2p*) erratum. Under very rare conditions, a faulty optimisation in the Cortex-A9 Store Buffer may lead to data corruption. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which disables the Store Buffer optimisation, preventing the defect from occurring. This has no visible impact on the overall performance or power consumption of the processor.
This option enables the workaround for the 751472 Cortex-A9 (prior to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB.
This option enables the workaround for the 754322 Cortex-A9 (r2p*, r3p*) erratum. A speculative memory access may cause a page table walk which starts prior to an ASID switch but completes afterwards. This can populate the micro-TLB with a stale entry which may be hit with the new ASID. This workaround places two dsb instructions in the mm switching code so that no page table walks can cross the ASID switch.
This option enables the workaround for the 754327 Cortex-A9 (prior to r2p0) erratum. The Store Buffer does not have any automatic draining mechanism and therefore a livelock may occur if an external agent continuously polls a memory location waiting to observe an update. This workaround defines cpu_relax() as smp_mb(), preventing correctly written polling loops from denying visibility of updates to memory.
This options enables the workaround for the 364296 ARM1136 r0p2 erratum (possible cache data corruption with hit-under-miss enabled). It sets the undocumented bit 31 in the auxiliary control register and the FI bit in the control register, thus disabling hit-under-miss without putting the processor into full low interrupt latency mode. ARM11MPCore is not affected.
This option enables the workaround for erratum 764369 affecting Cortex-A9 MPCore with two or more processors (all current revisions). Under certain timing circumstances, a data cache line maintenance operation by MVA targeting an Inner Shareable memory region may fail to proceed up to either the Point of Coherency or to the Point of Unification of the system. This workaround adds a DSB instruction before the relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU.
This option enables the workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance operation aborts with MMU exception, it might cause the processor to deadlock. This workaround puts DSB before executing ISB if an abort may occur on cache maintenance.
On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not adequately shooting down all use of the old entries. This option enables the Linux kernel workaround for this erratum which sends an IPI to the CPUs that are running the same ASID as the one being invalidated.
This option enables the workaround for the 773022 Cortex-A15 (up to r0p4) erratum. In certain rare sequences of code, the loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum.
This option enables the workaround for: - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM instruction might deadlock. Fixed in r0p1. - Cortex-A12 852422: Execution of a sequence of instructions might lead to either a data corruption or a CPU deadlock. Not fixed in any Cortex-A12 cores yet. This workaround for all both errata involves setting bit[12] of the Feature Register. This bit disables an optimisation applied to a sequence of 2 instructions that use opposing condition codes.
This option enables the workaround for the 821420 Cortex-A12 (all revs) erratum. In very rare timing conditions, a sequence of VMOV to Core registers instructions, for which the second one is in the shadow of a branch or abort, can lead to a deadlock when the VMOV instructions are issued out-of-order.
This option enables the workaround for the 825619 Cortex-A12 (all revs) erratum. Within rare timing constraints, executing a DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable and Device/Strongly-Ordered loads and stores might cause deadlock
This option enables the workaround for the 857271 Cortex-A12 (all revs) erratum. Under very rare timing conditions, the CPU might hang. The workaround is expected to have a < 1% performance impact.
This option enables the workaround for the 852421 Cortex-A17 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, execution of a DMB ST instruction might fail to properly order stores from GroupA and stores from GroupB.
This option enables the workaround for: - Cortex-A17 852423: Execution of a sequence of instructions might lead to either a data corruption or a CPU deadlock. Not fixed in any Cortex-A17 cores yet. This is identical to Cortex-A12 erratum 852422. It is a separate config option from the A12 erratum due to the way errata are checked for and handled.
This option enables the workaround for the 857272 Cortex-A17 erratum. This erratum is not known to be fixed in any A17 revision. This is identical to Cortex-A12 erratum 857271. It is a separate config option from the A12 erratum due to the way errata are checked for and handled.
Find out whether you have ISA slots on your motherboard. ISA is the name of a bus system, i.e. the way the CPU talks to the other stuff inside your box. Other bus systems are PCI, EISA, MicroChannel (MCA) or VESA. ISA is an older system, now being displaced by PCI; newer boards don't support it. If you have ISA, say Y, otherwise N.
Enable PCI on the BSE nanoEngine board.
The v7 ARM states that all cache and branch predictor maintenance operations that do not specify an address execute, relative to each other, in program order. However, because of this erratum, an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
This option should be selected by machines which have an SMP- capable CPU. The only effect of this option is to make the SMP-related options available to the user for configuration.
This enables support for systems with more than one CPU. If you have a system with only one CPU, say N. If you have a system with more than one CPU, say Y. If you say N here, the kernel will run on uni- and multiprocessor machines, but will use only one CPU of a multiprocessor machine. If you say Y here, the kernel will run on many, but not all, uniprocessor machines. On a uniprocessor machine, the kernel will run faster if you say N here. See also <file:Documentation/x86/i386/IO-APIC.rst>, <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at <http://tldp.org/HOWTO/SMP-HOWTO.html>. If you don't know what to do here, say N.
SMP kernels contain instructions which fail on non-SMP processors. Enabling this option allows the kernel to modify itself to make these instructions safe. Disabling it allows about 1K of space savings. If you don't know what to do here, say Y.
Support ARM cpu topology definition. The MPIDR register defines affinity between processors which is then used to describe the cpu topology of an ARM System.
Multi-core scheduler support improves the CPU scheduler's decision making when dealing with multi-core CPU chips at a cost of slightly increased overhead in some places. If unsure say N here.
Improves the CPU scheduler's decision making when dealing with MultiThreading at a cost of slightly increased overhead in some places. If unsure say N here.
This option enables support for the ARM snoop control unit
This option enables support for the ARM architected timer
This options enables support for the ARM timer and watchdog unit
This option provides the common power management infrastructure for (multi-)cluster based systems, such as big.LITTLE based systems.
To avoid wasting resources unnecessarily, MCPM only supports up to 2 clusters by default. Platforms with 3 or 4 clusters that use MCPM must select this option to allow the additional clusters to be managed.
This option enables support selections for the big.LITTLE system architecture.
The big.LITTLE "switcher" provides the core functionality to transparently handle transition between a cluster of A15's and a cluster of A7's in a big.LITTLE system.
This is a simple and dummy char dev interface to control the big.LITTLE switcher core code. It is meant for debugging purposes only.
Select the desired split between kernel and user memory. If you are not absolutely sure what you are doing, leave this option alone! config VMSPLIT_3G bool "3G/1G user/kernel split" config VMSPLIT_3G_OPT depends on !ARM_LPAE bool "3G/1G user/kernel split (for full 1G low memory)" config VMSPLIT_2G bool "2G/2G user/kernel split" config VMSPLIT_1G bool "1G/3G user/kernel split"
The maximum number of CPUs that the kernel can support. Up to 32 CPUs can be supported, or up to 16 if kmap_local() debugging is enabled, which uses half of the per-CPU fixmap slots as guard regions.
Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu.
Say Y here if you want Linux to communicate with system firmware
implementing the PSCI specification for CPU-centric power
management operations described in ARM document number ARM DEN
0022A ("Power State Coordination Interface System Software on
ARM processors").
Maximum number of GPIOs in the system. If unsure, leave the default value.
By enabling this option, the kernel will be compiled in Thumb-2 mode. If unsure, say N.
The ARM compiler inserts calls to __aeabi_idiv() and __aeabi_uidiv() when it needs to perform division on signed and unsigned integers. Some v7 CPUs have support for the sdiv and udiv instructions that can be used to implement those functions. Enabling this option allows the kernel to modify itself to replace the first two instructions of these library functions with the sdiv or udiv plus "bx lr" instructions when the CPU it is running on supports them. Typically this will be faster and less power intensive than running the original library code to do integer division.
This option allows for the kernel to be compiled using the latest ARM ABI (aka EABI). This is only useful if you are using a user space environment that is also compiled with EABI. Since there are major incompatibilities between the legacy ABI and EABI, especially with regard to structure member alignment, this option also changes the kernel syscall calling convention to disambiguate both ABIs and allow for backward compatibility support (selected with CONFIG_OABI_COMPAT). To use this you need GCC version 4.0.0 or later.
This option preserves the old syscall interface along with the new (ARM EABI) one. It also provides a compatibility layer to intercept syscalls that have structure arguments which layout in memory differs between the legacy ABI and the new ARM EABI (only for non "thumb" binaries). This option adds a tiny overhead to all syscalls and produces a slightly larger kernel. The seccomp filter system will not be available when this is selected, since there is no way yet to sensibly distinguish between calling conventions during filtering. If you know you'll be using only pure EABI user space then you can say N here. If this option is not selected and you attempt to execute a legacy ABI binary then the result will be UNPREDICTABLE (in fact it can be predicted that it won't work at all). If in doubt say N.
The address space of ARM processors is only 4 Gigabytes large and it has to accommodate user address space, kernel address space as well as some memory mapped IO. That means that, if you have a large amount of physical memory and/or IO, not all of the memory can be "permanently mapped" by the kernel. The physical memory that is not permanently mapped is called "high memory". Depending on the selected kernel/user memory split, minimum vmalloc space and actual amount of RAM, you may not need this option which should result in a slightly faster kernel. If unsure, say n.
The VM uses one page of physical memory for each page table. For systems with a lot of processes, this can use a lot of precious low memory, eventually leading to low memory being consumed by page tables. Setting this option will allow user-space 2nd level page tables to reside in high memory.
Increase kernel security by ensuring that normal kernel accesses are unable to access userspace addresses. This can help prevent use-after-free bugs becoming an exploitable privilege escalation by ensuring that magic values (such as LIST_POISON) will always fault when dereferenced. CPUs with low-vector mappings use a best-efforts implementation. Their lower 1MB needs to remain accessible for the vectors, but the remainder of userspace will become appropriately inaccessible.
Allocate PLTs when loading modules so that jumps and calls whose targets are too far away for their relative offsets to be encoded in the instructions themselves can be bounced via veneers in the module's PLT. This allows modules to be allocated in the generic vmalloc area after the dedicated module memory area has been exhausted. The modules will use slightly more memory, but after rounding up to page size, the actual memory footprint is usually the same. Disabling this is usually safe for small single-platform configurations. If unsure, say y.
The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of pages. This option selects the largest power of two that the kernel keeps in the memory allocator. If you need to allocate very large blocks of physically contiguous memory, then you may need to increase this value. This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages.
ARM processors cannot fetch/store information which is not naturally aligned on the bus, i.e., a 4 byte fetch must start at an address divisible by 4. On 32-bit ARM processors, these non-aligned fetch/store instructions will be emulated in software if you say here, which has a severe performance impact. This is necessary for correct operation of some network protocols. With an IP-only configuration it is safe to say N, otherwise say Y.
Implement faster copy_to_user and clear_user methods for CPU cores where a 8-word STM instruction give significantly higher memory write throughput than a sequence of individual 32bit stores. A possible side effect is a slight increase in scheduling latency between threads sharing the same address space if they invoke such copy operations with large buffers. However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain.
This changes the kernel so it can modify itself when it is run under a hypervisor, potentially improving performance significantly over full virtualization.
Select this option to enable fine granularity task steal time accounting. Time spent executing other tasks in parallel with the current vCPU is discounted from the vCPU power. To account for that, there can be a small performance impact. If in doubt, say N here.
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
Due to the fact that GCC uses an ordinary symbol reference from which to load the value of the stack canary, this value can only change at reboot time on SMP systems, and all tasks running in the kernel's address space are forced to use the same canary value for the entire duration that the system is up. Enable this option to switch to a different method that uses a different canary value for each task.
Include support for flattened device tree machine descriptions.
This is the traditional way of passing data to the kernel at boot time. If you are solely relying on the flattened device tree (or the ARM_ATAG_DTB_COMPAT option) then you may unselect this option to remove ATAGS support from your kernel binary. If unsure, leave this to y.
This was deprecated in 2001 and announced to live on for 5 years. Some old boot loaders still use this way.
The physical address at which the ROM-able zImage is to be placed in the target. Platforms which normally make use of ROM-able zImage formats normally set this to a suitable value in their defconfig file. If ZBOOT_ROM is not enabled, this has no effect.
The base address of an area of read/write memory in the target for the ROM-able zImage which must be available while the decompressor is running. It must be large enough to hold the entire decompressed kernel plus an additional 128 KiB. Platforms which normally make use of ROM-able zImage formats normally set this to a suitable value in their defconfig file. If ZBOOT_ROM is not enabled, this has no effect.
Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N.
With this option, the boot code will look for a device tree binary (DTB) appended to zImage (e.g. cat zImage <filename>.dtb > zImage_w_dtb). This is meant as a backward compatibility convenience for those systems with a bootloader that can't be upgraded to accommodate the documented boot protocol using a device tree. Beware that there is very little in terms of protection against this option being confused by leftover garbage in memory that might look like a DTB header after a reboot if no actual DTB is appended to zImage. Do not leave this option active in a production kernel if you don't intend to always append a DTB. Proper passing of the location into r2 of a bootloader provided DTB is always preferable to this option.
Some old bootloaders can't be updated to a DTB capable one, yet they provide ATAGs with memory configuration, the ramdisk address, the kernel cmdline string, etc. Such information is dynamically provided by the bootloader and can't always be stored in a static DTB. To allow a device tree enabled kernel to be used with such bootloaders, this option allows zImage to extract the information from the ATAG list and store it at run time into the appended DTB.
Uses the command-line options passed by the boot loader instead of the device tree bootargs property. If the boot loader doesn't provide any, the device tree bootargs property will be used.
The command-line arguments provided by the boot loader will be appended to the the device tree bootargs property.
On some architectures (e.g. CATS), there is currently no way for the boot loader to pass arguments to the kernel. For these architectures, you should supply some command-line options at build time by entering them here. As a minimum, you should specify the memory size and the root device (e.g., mem=64M root=/dev/nfs).
Uses the command-line options passed by the boot loader. If the boot loader doesn't provide any, the default kernel command string provided in CMDLINE will be used.
The command-line arguments provided by the boot loader will be appended to the default kernel command string.
Always use the default kernel command string, even if the boot loader passes other arguments to the kernel. This is useful if you cannot or don't want to change the command-line options your boot loader passes to the kernel.
Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM space since the text section of the kernel is not loaded from flash to RAM. Read-write sections, such as the data section and stack, are still copied to RAM. The XIP kernel is not compressed since it has to run directly from flash, so it will take more space to store it. The flash address used to link the kernel object files, and for storing it, is configuration dependent. Therefore, if you say Y here, you must know the proper physical address where to store the kernel image depending on your own flash memory usage. Also note that the make target becomes "make xipImage" rather than "make zImage" or "make Image". The final kernel binary to put in ROM memory will be arch/arm/boot/xipImage. If unsure, say N.
This is the physical address in your flash memory the kernel will be linked for and stored to. This address is dependent on your own flash usage.
Before the kernel is actually executed, its .data section has to be copied to RAM from ROM. This option allows for storing that data in compressed form and decompressed to RAM rather than merely being copied, saving some precious ROM space. A possible drawback is a slightly longer boot delay.
kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot but it is independent of the system firmware. And like a reboot you can start any kernel with it, not just Linux. It is an ongoing process to be certain the hardware in a machine is properly shutdown, so do not be surprised if this code does not initially work for you.
Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec.
Generate crash dump after being started by kexec. This should be normally only set in special crash dump kernels which are loaded in the main kernel with kexec-tools into a specially reserved region and then later executed after a crash by kdump/kexec. The crash dump kernel must be compiled to a memory address not used by the main kernel For more details see Documentation/admin-guide/kdump/kdump.rst
ZRELADDR is the physical address where the decompressed kernel image will be placed. If AUTO_ZRELADDR is selected, the address will be determined at run-time, either by masking the current IP with 0xf8000000, or, if invalid, from the DTB passed in r2. This assumes the zImage being placed in the first 128MB from start of memory.
This option provides support for runtime services provided by UEFI firmware (such as non-volatile variables, realtime clock, and platform reset). A UEFI stub is also provided to allow the kernel to be booted as an EFI application. This is only useful for kernels that may run on systems that have UEFI firmware.
This enables SMBIOS/DMI feature for systems. This option is only useful on systems that have UEFI firmware. However, even with this option, the resultant kernel should continue to boot on existing non-UEFI platforms. NOTE: This does *NOT* enable or encourage the use of DMI quirks, i.e., the the practice of identifying the platform via DMI to decide whether certain workarounds for buggy hardware and/or firmware need to be enabled. This would require the DMI subsystem to be enabled much earlier than we do on ARM, which is non-trivial.
Say Y to include the NWFPE floating point emulator in the kernel. This is necessary to run most binaries. Linux does not currently support floating point hardware so you need to say Y here even if your machine has an FPA or floating point co-processor podule. You may say N here if you are going to load the Acorn FPEmulator early in the bootup.
Say Y to include 80-bit support in the kernel floating-point emulator. Otherwise, only 32 and 64-bit support is compiled in. Note that gcc does not generate 80-bit operations by default, so in most cases this option only enlarges the size of the floating point emulator without any good reason. You almost surely want to say N here.
Say Y here to include the FAST floating point emulator in the kernel. This is an experimental much faster emulator which now also has full precision for the mantissa. It does not support any exceptions. It is very simple, and approximately 3-6 times faster than NWFPE. It should be sufficient for most programs. It may be not suitable for scientific calculations, but you have to check this for yourself. If you do not feel you need a faster FP emulation you should better choose NWFPE.
Say Y to include VFP support code in the kernel. This is needed if your hardware includes a VFP unit. Please see <file:Documentation/arm/vfp/release-notes.rst> for release notes and additional status information. Say N if your target does not have VFP hardware.
Say Y to include support code for NEON, the ARMv7 Advanced SIMD Extension.
Say Y to include support for NEON in kernel mode.