A 32-bit RISC microprocessor based on the ARM7 processor core which has no memory control unit and cache. Say Y if you want support for the ARM7TDMI processor. Otherwise, say N.
A 32-bit RISC processor with 8kByte Cache, Write Buffer and MMU built around an ARM7TDMI core. Say Y if you want support for the ARM720T processor. Otherwise, say N.
A 32-bit RISC processor with 8KB cache or 4KB variants, write buffer and MPU(Protection Unit) built around an ARM7TDMI core. Say Y if you want support for the ARM740T processor. Otherwise, say N.
A 32-bit RISC microprocessor based on the ARM9 processor core which has no memory control unit and cache. Say Y if you want support for the ARM9TDMI processor. Otherwise, say N.
The ARM920T is licensed to be produced by numerous vendors, and is used in the Cirrus EP93xx and the Samsung S3C2410. Say Y if you want support for the ARM920T processor. Otherwise, say N.
The ARM922T is a version of the ARM920T, but with smaller instruction and data caches. It is used in Altera's Excalibur XA device family and the ARM Integrator. Say Y if you want support for the ARM922T processor. Otherwise, say N.
The ARM925T is a mix between the ARM920T and ARM926T, but with different instruction and data caches. It is used in TI's OMAP device family. Say Y if you want support for the ARM925T processor. Otherwise, say N.
This is a variant of the ARM920. It has slightly different instruction sequences for cache and TLB operations. Curiously, there is no documentation on it at the ARM corporate website. Say Y if you want support for the ARM926T processor. Otherwise, say N.
The FA526 is a version of the ARMv4 compatible processor with Branch Target Buffer, Unified TLB and cache line size 16. Say Y if you want support for the FA526 processor. Otherwise, say N.
ARM940T is a member of the ARM9TDMI family of general- purpose microprocessors with MPU and separate 4KB instruction and 4KB data cases, each with a 4-word line length. Say Y if you want support for the ARM940T processor. Otherwise, say N.
ARM946E-S is a member of the ARM9E-S family of high- performance, 32-bit system-on-chip processor solutions. The TCM and ARMv5TE 32-bit instruction set is supported. Say Y if you want support for the ARM946E-S processor. Otherwise, say N.
The ARM1020 is the 32K cached version of the ARM10 processor, with an addition of a floating-point unit. Say Y if you want support for the ARM1020 processor. Otherwise, say N.
The ARM1022E is an implementation of the ARMv5TE architecture based upon the ARM10 integer core with a 16KiB L1 Harvard cache, embedded trace macrocell, and a floating-point unit. Say Y if you want support for the ARM1022E processor. Otherwise, say N.
The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture based upon the ARM10 integer core. Say Y if you want support for the ARM1026EJ-S processor. Otherwise, say N.
The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and is available at five speeds ranging from 100 MHz to 233 MHz. More information is available at <http://developer.intel.com/design/strong/sa110.htm>. Say Y if you want support for the SA-110 processor. Otherwise, say N.
This enables the usage of some old Feroceon cores for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and early Feroceon-2850.
Select this if your CPU doesn't support the 32 bit ARM instructions.
Select this if your CPU can support Thumb mode.
ARM Architecture Version 4 TLB with writethrough cache.
ARM Architecture Version 4 TLB with writeback cache.
ARM Architecture Version 4 TLB with writeback cache and invalidate instruction cache entry.
Feroceon TLB (v4wbi with non-outer-cachable page table walks).
Faraday ARM FA526 architecture, unified TLB with writeback cache and invalidate instruction cache entry. Branch target buffer is also supported.
This indicates whether the CPU has the ASID register; used to tag TLB and possibly cache entries.
Processor has the CP15 register.
Processor has the CP15 register, which has MMU related registers.
Processor has the CP15 register, which has MPU related registers.
This option enables or disables the use of domain switching via the set_fs() function.
This option indicates the number of interrupts connected to the NVIC. The value can be larger than the real number of interrupts supported by the system, but must not be lower. The default value is 240, corresponding to the maximum number of interrupts supported by the NVIC on Cortex-M family. If unsure, keep default value.
Say Y if you have an ARMv7 processor supporting the LPAE page table format and you would like to access memory beyond the 4GB limit. The resulting kernel image will not run on processors without the LPA extension. If unsure, say N.
Say Y if you want to include kernel support for running user space Thumb binaries. The Thumb instruction set is a compressed form of the standard ARM instruction set resulting in smaller binaries at the expense of slightly less efficient code. If this option is disabled, and you run userspace that switches to Thumb mode, signal handling will not work correctly, resulting in segmentation faults or illegal instruction aborts. If you don't know what this all is, saying Y is a safe choice.
Say Y here if you have a CPU with the ThumbEE extension and code to make use of it. Say N for code that can run on CPUs without ThumbEE.
Enable the kernel to make use of the ARM Virtualization Extensions to install hypervisors without run-time firmware assistance. A compliant bootloader is required in order to make maximum use of this feature. Refer to Documentation/arm/booting.rst for details.
ARMv6 architecture deprecates use of the SWP/SWPB instructions. ARMv7 multiprocessing extensions introduce the ability to disable these instructions, triggering an undefined instruction exception when executed. Say Y here to enable software emulation of these instructions for userspace (not kernel) using LDREX/STREX. Also creates /proc/cpu/swp_emulation for statistics. In some older versions of glibc [<=2.8] SWP is used during futex trylock() operations with the assumption that the code will not be preempted. This invalid assumption may be more likely to fail with SWP emulation enabled, leading to deadlock of the user application. NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external transaction monitoring block called a global monitor to maintain update atomicity. If your system does not implement a global monitor, this option can cause programs that perform SWP operations to uncached memory to deadlock. If unsure, say Y.
Say Y if you plan on running a kernel in big-endian mode. Note that your board must be properly built and your board port must properly enable any big-endian related features of your chipset/board/processor.
Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
Say Y here to select high exception vector(0xFFFF0000~). The exception vector can vary depending on the platform design in nommu mode. If your platform needs to select high exception vector, say Y. Otherwise or if you are unsure, say N, and the low exception vector (0x00000000~) will be used.
Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N.
Some big.LITTLE systems have I-Cache line size mismatch between LITTLE and big cores. Say Y here to enable a workaround for proper I-Cache support on such systems. If unsure, say N.
Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N.
Some cores are synthesizable to have various sized cache. For ARM946E-S case, it can vary from 0KB to 1MB. To support such cache operations, it is efficient to know the size before compile time. If your SoC is configured to have a different size, define the value here with proper conditions.
Say Y here to use the data cache in writethrough mode. Unless you specifically require this or are unsure, say N.
Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N.
Say Y here to disable branch prediction. If unsure, say N.
Speculation attacks against some high-performance processors rely on being able to manipulate the branch predictor for a victim context by executing aliasing branches in the attacker context. Such attacks can be partially mitigated against by clearing internal branch predictor state and limiting the prediction logic in some situations. This config option will take CPU-specific actions to harden the branch predictor against aliasing attacks and may rely on specific instruction sequences or control bits being set by the system firmware. If unsure, say Y.
An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that required register must be emulated.
Warning: disabling this option may break user programs. Provide kuser helpers in the vector page. The kernel provides helper code to userspace in read only form at a fixed location in the high vector page to allow userspace to be independent of the CPU type fitted to the system. This permits binaries to be run on ARMv4 through to ARMv7 without modification. See Documentation/arm/kernel_user_helpers.rst for details. However, the fixed address nature of these helpers can be used by ROP (return orientated programming) authors when creating exploits. If all of the binaries and libraries which run on your platform are built specifically for your platform, and make no use of these helpers, then you can turn this option off to hinder such exploits. However, in that case, if a binary or library relying on those helpers is run, it will receive a SIGILL signal, which will terminate the program. Say N here only if you are absolutely certain that you do not need these helpers; otherwise, the safe option is to say Y.
Place in the process address space an ELF shared object providing fast implementations of gettimeofday and clock_gettime. Systems that implement the ARM architected timer will receive maximum benefit. You must have glibc 2.22 or later for programs to seamlessly take advantage of this.
The Snoop Control Unit on ARM11MPCore does not detect the
cache maintenance operations and the dma_{map,unmap}_area()
functions may leave stale cache entries on other CPUs. By
enabling this option, Read or Write For Ownership in the ARMv6
DMA cache maintenance functions is performed. These LDR/STR
instructions change the cache line state to shared or modified
so that the cache operation has the desired effect.
Note that the workaround is only valid on processors that do
not perform speculative loads into the D-cache. For such
processors, if cache maintenance operations are not broadcast
in hardware, other workarounds are needed (e.g. cache
maintenance broadcasting in software via FIQ).
The outer cache has a outer_cache_fns.sync function pointer that can be used to drain the write buffer of the outer cache.
This option enables the Broadcom Brahma-B15 read-ahead cache controller. If disabled, the read-ahead cache remains off.
This option enables the Feroceon L2 cache controller.
Say Y here to use the Feroceon L2 cache in writethrough mode. Unless you specifically require this, say N for writeback mode.
This option should be selected by machines which have a L2x0 or PL310 cache controller, but where its use is optional. The only effect of this option is to make CACHE_L2X0 and related options available to the user for configuration. Boards or SoCs which always require the cache controller support to be present should select CACHE_L2X0 directly instead of this option, thus preventing the user from inadvertently configuring a broken kernel.
This option enables the L2x0 PrimeCell.
This option enables support for the performance monitoring features of the L220 and PL310 outer cache controllers.
The PL310 L2 cache controller implements three types of Clean & Invalidate maintenance operations: by Physical Address (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). They are architecturally defined to behave as the execution of a clean operation followed immediately by an invalidate operation, both performing to the same memory location. This functionality is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) as clean lines are not invalidated as a result of these operations.
PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Revisions prior to r3p1 are affected by this errata (fixed in r3p1).
This option enables the workaround for the 753970 PL310 (r3p0) erratum. Under some condition the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. The workaround is to replace the normal offset of cache sync operation (0x730) by another offset targeting an unmapped PL310 register 0x740. This has the same effect as the cache sync operation: store buffer drain and waiting for all buffers empty.
On revisions of the PL310 prior to r3p2, the Store Buffer does not automatically drain. This can cause normal, non-cacheable writes to be retained when the memory system is idle, leading to suboptimal I/O performance for drivers using coherent DMA. This option adds a write barrier to the cpu_idle loop so that, on systems with an outer cache, the store buffer is drained explicitly.
This option enables the Tauros2 L2 cache controller (as found on PJ1/PJ4).
This option enables the UniPhier outer cache (system cache) controller.
This option enables the L2 cache on XScale3.
Setting ARM L1 cache line size to 64 Bytes.
Setting ARM L1 cache line size to 128 Bytes.
Historically, the kernel has used strongly ordered mappings to provide DMA coherent memory. With the advent of ARMv7, mapping memory with differing types results in unpredictable behaviour, so on these CPUs, this option is forced on. Multiple mappings with differing attributes is also unpredictable on ARMv6 CPUs, but since they do not have aggressive speculative prefetch, no harm appears to occur. However, drivers may be missing the necessary barriers for ARMv6, and therefore turning this on may result in unpredictable driver behaviour. Therefore, we offer this as an option. On some of the beefier ARMv7-M machines (with DMA and write buffers) you likely want this enabled, while those that didn't need it until now also won't need it in the future. You are recommended say 'Y' here and debug any affected drivers.
This option specifies the architecture can support big endian operation.
If this is set, rodata will be made explicitly non-executable. This provides protection on the rare chance that attackers might find and use ROP gadgets that exist in the rodata section. This adds an additional section-aligned split of rodata from kernel text so it can be made explicitly non-executable. This padding may waste memory space to gain the additional protection.