Say Y here to choose from a selection of cryptographic algorithms implemented using ARM specific CPU features or instructions.
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented using optimized ARM assembler.
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented using optimized ARM NEON assembly, when NEON instructions are available.
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented using special ARMv8 Crypto Extensions.
SHA-256 secure hash standard (DFIPS 180-2) implemented using special ARMv8 Crypto Extensions.
SHA-256 secure hash standard (DFIPS 180-2) implemented using optimized ARM assembler and NEON, when available.
SHA-512 secure hash standard (DFIPS 180-2) implemented using optimized ARM assembler and NEON, when available.
BLAKE2s digest algorithm optimized with ARM scalar instructions. This is faster than the generic implementations of BLAKE2s and BLAKE2b, but slower than the NEON implementation of BLAKE2b. (There is no NEON implementation of BLAKE2s, since NEON doesn't really help with it.)
BLAKE2b digest algorithm optimized with ARM NEON instructions. On ARM processors that have NEON support but not the ARMv8 Crypto Extensions, typically this BLAKE2b implementation is much faster than SHA-2 and slightly faster than SHA-1.
Use optimized AES assembler routines for ARM platforms. On ARM processors without the Crypto Extensions, this is the fastest AES implementation for single blocks. For multiple blocks, the NEON bit-sliced implementation is usually faster. This implementation may be vulnerable to cache timing attacks, since it uses lookup tables. However, as countermeasures it disables IRQs and preloads the tables; it is hoped this makes such attacks very difficult.
Use a faster and more secure NEON based implementation of AES in CBC, CTR and XTS modes Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode and for XTS mode encryption, CBC and XTS mode decryption speedup is around 25%. (CBC encryption speed is not affected by this driver.) This implementation does not rely on any lookup tables so it is believed to be invulnerable to cache timing attacks.
Use an implementation of AES in CBC, CTR and XTS modes that uses ARMv8 Crypto Extensions
Use an implementation of GHASH (used by the GCM AEAD chaining mode) that uses the 64x64 to 128 bit polynomial multiplication (vmull.p64) that is part of the ARMv8 Crypto Extensions, or a slower variant that uses the vmull.p8 instruction that is part of the basic NEON ISA.