Xtensa processors are 32-bit RISC machines designed by Tensilica primarily for embedded systems. These processors are both configurable and extensible. The Linux port to the Xtensa architecture supports all processor configurations and extensions, with reasonable minimum requirements. The Xtensa Linux project has a home page at <http://www.linux-xtensa.org/>.
This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
Select this variant to use a custom Xtensa processor configuration. You will be prompted for a processor variant CORENAME.
Provide the name of a custom Xtensa processor variant. This CORENAME selects arch/xtensa/variant/CORENAME. Don't forget you have to select MMU if you have one.
Build a Conventional Kernel with full MMU support, ie: it supports a TLB with auto-loading, page protection.
Enable if core variant has Performance Monitor Module with External Registers Interface. If unsure, say N.
If PMM IRQ is the only IRQ at EXCM level it is safe to treat it as NMI, which improves accuracy of profiling. If there are other interrupts at or above PMM IRQ priority level but not above the EXCM level, PMM IRQ still may be treated as NMI, but only if these IRQs are not used. There will be a build warning saying that this is not safe, and a bugcheck if one of these IRQs actually fire. If unsure, say N.
The Xtensa architecture currently does not handle unaligned memory accesses in hardware but through an exception handler. Per default, unaligned memory accesses are disabled in user space. Say Y here to enable unaligned memory access in user space.
This option is used to indicate that the system-on-a-chip (SOC) supports Multiprocessing. Multiprocessor support implemented above the CPU core definition and currently needs to be selected manually. Multiprocessor support is implemented with external cache and interrupt controllers. The MX interrupt distributer adds Interprocessor Interrupts and causes the IRQ numbers to be increased by 4 for devices like the open cores ethernet driver and the serial interface. You still have to select "Enable SMP" to enable SMP on this SOC.
Enabled SMP Software; allows more than one CPU/CORE to be activated during startup.
Say Y here to allow turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. Say N if you want to disable CPU hotplug.
fast_syscall_xtensa is a syscall that can make atomic operations on UP kernel when processor has no s32c1i support. This syscall is deprecated. It may have issues when called with invalid arguments. It is provided only for backwards compatibility. Only enable it if your userspace software requires it. If unsure, say N.
fast_syscall_spill_registers is a syscall that spills all active register windows of a calling userspace task onto its stack. This syscall is deprecated. It may have issues when called with invalid arguments. It is provided only for backwards compatibility. Only enable it if your userspace software requires it. If unsure, say N.
Select supported userspace ABI. If unsure, choose the default ABI.
Assume default userspace ABI. For XEA2 cores it is windowed ABI. call0 ABI binaries may be run on such kernel, but signal delivery will not work correctly for them.
Select this option to support only call0 ABI in userspace. Windowed ABI binaries will crash with a segfault caused by an illegal instruction exception on the first 'entry' opcode. Choose this option if you're planning to run only user code built with call0 ABI.
Select this option to support both windowed and call0 userspace ABIs. When enabled all processes are started with PS.WOE disabled and a fast user exception handler for an illegal instruction is used to turn on PS.WOE bit on the first 'entry' opcode executed by the userspace. This option should be enabled for the kernel that must support both call0 and windowed ABIs in userspace at the same time. Note that Xtensa ISA does not guarantee that entry opcode will raise an illegal instruction exception on cores with XEA2 when PS.WOE is disabled, check whether the target core supports it.
On some platforms (XT2000, for example), the CPU clock rate can vary. The frequency can be determined, however, by measuring against a well known, fixed frequency, such as an UART oscillator.
ISS is an acronym for Tensilica's Instruction Set Simulator.
XT2000 is the name of Tensilica's feature-rich emulation platform. This hardware is capable of running a full Linux distribution.
XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). This hardware is capable of running a full Linux distribution.
The BogoMIPS value can easily be derived from the CPU frequency.
On some architectures (EBSA110 and CATS), there is currently no way for the boot loader to pass arguments to the kernel. For these architectures, you should supply some command-line options at build time by entering them here. As a minimum, you should specify the memory size and the root device (e.g., mem=64M root=/dev/nfs).
Include support for flattened device tree machine descriptions.
Parse parameters passed to the kernel from the bootloader. It may be disabled if the kernel is known to run without the bootloader. If unsure, say Y.
Choose semihosting interface that will be used for serial port, block device and networking.
Use simcall instruction. simcall is only available on simulators, it does nothing on hardware.
Use break instruction. It is available on real hardware when GDB is attached to it via JTAG.
Create block devices that map to files in the host file system. Device binding to host file may be changed at runtime via proc interface provided the device is not in use.
This is the default minimal number of created block devices. Kernel/module parameter 'simdisk_count' may be used to change this value at runtime. More file names (but no more than 10) may be specified as parameters, simdisk_count grows accordingly.
Attach a first simdisk to a host file. Conventionally, this file contains a root file system.
Another simulated disk in a host file for a buildroot-independent storage.
There's a 2x16 LCD on most of XTFPGA boards, kernel may output progress messages there during bootup/shutdown. It may be useful during board bringup. If unsure, say N.
Base address of the LCD controller inside KIO region. Different boards from XTFPGA family have LCD controller at different addresses. Please consult prototyping user guide for your board for the correct address. Wrong address here may lead to hardware lockup.
LCD may be connected with 4- or 8-bit interface, 8-bit access may only be used with 8-bit interface. Please consult prototyping user guide for your board for the correct interface width.
Earlier version initialized the MMU in the exception vector before jumping to _startup in head.S and had an advantage that it was possible to place a software breakpoint at 'reset' and then enter your normal kernel breakpoints once the MMU was mapped to the kernel mappings (0XC0000000). This unfortunately won't work for U-Boot and likely also won't work for using KEXEC to have a hot kernel ready for doing a KDUMP. So now the MMU is initialized in head.S but it's necessary to use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. xt-gdb can't place a Software Breakpoint in the 0XD region prior to mapping the MMU and after mapping even if the area of low memory was mapped gdb wouldn't remove the breakpoint on hitting it as the PC wouldn't match. Since Hardware Breakpoints are recommended for Linux configurations it seems reasonable to just assume they exist and leave this older mechanism for unfortunate souls that choose not to follow Tensilica's recommendation. Selecting this will cause U-Boot to set the KERNEL Load and Entry address at 0x00003000 instead of the mapped std of 0xD0003000. If in doubt, say Y.
Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM space since the text section of the kernel is not loaded from flash to RAM. Read-write sections, such as the data section and stack, are still copied to RAM. The XIP kernel is not compressed since it has to run directly from flash, so it will take more space to store it. The flash address used to link the kernel object files, and for storing it, is configuration dependent. Therefore, if you say Y here, you must know the proper physical address where to store the kernel image depending on your own flash memory usage. Also note that the make target becomes "make xipImage" rather than "make Image" or "make uImage". The final kernel binary to put in ROM memory will be arch/xtensa/boot/xipImage. If unsure, say N.
These cache attributes are set up for noMMU systems. Each hex digit specifies cache attributes for the corresponding 512MB memory region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. Cache attribute values are specific for the MMU type. For region protection MMUs: 1: WT cached, 2: cache bypass, 4: WB cached, f: illegal. For full MMU: bit 0: executable, bit 1: writable, bits 2..3: 0: cache bypass, 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is reserved). For MPU: 0: illegal, 1: WB cache, 2: WB, no-write-allocate cache, 3: WT cache, 4: cache bypass.
This is the physical address where KSEG is mapped. Please refer to the chosen KSEG layout help for the required address alignment. Unpacked kernel image (including vectors) must be located completely within KSEG. Physical memory below this address is not available to linux. If unsure, leave the default value here.
This is the virtual address where the XIP kernel is mapped. XIP kernel may be mapped into KSEG or KIO region, virtual address provided here must match kernel load address provided in KERNEL_LOAD_ADDRESS.
This is the address where the kernel is loaded. It is virtual address for MMUv2 configurations and physical address for all other configurations. If unsure, leave the default value here.
Choose whether relocatable vectors are merged into the kernel .text or placed separately at runtime. This option does not affect configurations without VECBASE register where vectors are always placed at their hardware-defined locations.
This option puts relocatable vectors into the kernel .text section with proper alignment. This is a safe choice for most configurations.
This option puts relocatable vectors at specific virtual address. Vectors are merged with the .init data in the kernel image and are copied into their designated location during kernel startup. Use it to put vectors into IRAM or out of FLASH on kernels with XIP-aware MTD support.
This is the virtual address of the (relocatable) vectors base. It must be within KSEG if MMU is used.
This is the virtual address where XIP kernel data is copied. It must be within KSEG if MMU is used.
This is the base address used for both PAGE_OFFSET and PHYS_OFFSET in noMMU configurations. If unsure, leave the default value here.
MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 without cache. KSEG_PADDR must be aligned to 128MB.
TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 with cache and to 0xc0000000 without cache. KSEG_PADDR must be aligned to 256MB.
TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 with cache and to 0xc0000000 without cache. KSEG_PADDR must be aligned to 256MB.
Linux can use the full amount of RAM in the system by default. However, the default MMUv2 setup only maps the lowermost 128 MB of memory linearly to the areas starting at 0xd0000000 (cached) and 0xd8000000 (uncached). When there are more than 128 MB memory in the system not all of it can be "permanently mapped" by the kernel. The physical memory that's not permanently mapped is called "high memory". If you are compiling a kernel which will never run on a machine with more than 128 MB total physical RAM, answer N here. If unsure, say Y.
The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of pages. This option selects the largest power of two that the kernel keeps in the memory allocator. If you need to allocate very large blocks of physically contiguous memory, then you may need to increase this value. This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages.