Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to boot on these systems, this option must not be set. On other systems (such as the SH-3 and 4) where an MMU exists, turning this off will boot the kernel on these machines with the MMU implicitly switched off.
The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of pages. This option selects the largest power of two that the kernel keeps in the memory allocator. If you need to allocate very large blocks of physically contiguous memory, then you may need to increase this value. This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages. The page size is not necessarily 4KB. Keep this in mind when choosing a value for this option.
Computers built with Hitachi SuperH processors always map the ROM starting at address zero. But the processor does not specify the range that RAM takes. The physical memory (RAM) start address will be automatically set to 08000000. Other platforms, such as the Solution Engine boards typically map RAM at 0C000000. Tweak this only when porting to a new machine which does not already have a defconfig. Changing it from the known correct value on any of the known systems will only lead to disaster.
This sets the default memory size assumed by your SH kernel. It can be overridden as normal by the 'mem=' argument on the kernel command line. If unsure, consult your board specifications or just leave it as 0x04000000 which was the default value before this became configurable.
If you say Y here, physical addressing will be extended to 32-bits through the SH-4A PMB. If this is not set, legacy 29-bit physical addressing will be used.
This will enable support for the kernel mapping a vDSO page in process space, and subsequently handing down the entry point to the libc through the ELF auxiliary vector. From the kernel side this is used for the signal trampoline. For systems with an MMU that can afford to give up a page, (the default value) say Y.
Some SH systems have many various memories scattered around the address space, each with varying latencies. This enables support for these blocks by binding them to nodes and allowing memory policies to be used for prioritizing and controlling allocation behaviour.
This is the default page size used by all SuperH CPUs.
This enables 8kB pages as supported by SH-X2 and later MMUs.
This enables 16kB pages on MMU-less SH systems.
This enables support for 64kB pages, possible on all SH-4 CPUs and later.
Multi-core scheduler support improves the CPU scheduler's decision making when dealing with multi-core CPU chips at a cost of slightly increased overhead in some places. If unsure say N here.
Selecting this option will configure the caches in write-through mode, as opposed to the default write-back configuration. Since there's sill some aliasing issues on SH-4, this option will unfortunately still require the majority of flushing functions to be implemented to deal with aliasing. If unsure, say N.