arch/riscv/Kconfig.erratas v5.13-rc1

Menu: CPU errata selection

RISCV_ERRATA_ALTERNATIVE

RISC-V alternative scheme

This Kconfig allows the kernel to automatically patch the
errata required by the execution platform at run time. The
code patching is performed once in the boot stages. It means
that the overhead from this mechanism is just taken once.

ERRATA_SIFIVE

SiFive errata

All SiFive errata Kconfig depend on this Kconfig. Disabling
this Kconfig will disable all SiFive errata. Please say "Y"
here if your platform uses SiFive CPU cores.

Otherwise, please say "N" here to avoid unnecessary overhead.

ERRATA_SIFIVE_CIP_453

Apply SiFive errata CIP-453

This will apply the SiFive CIP-453 errata to add sign extension
to the $badaddr when exception type is instruction page fault
and instruction access fault.

If you don't know what to do here, say "Y".

ERRATA_SIFIVE_CIP_1200

Apply SiFive errata CIP-1200

This will apply the SiFive CIP-1200 errata to repalce all
"sfence.vma addr" with "sfence.vma" to ensure that the addr
has been flushed from TLB.

If you don't know what to do here, say "Y".