MPC86XADS

MPC86XADS

MPC86x Application Development System by Freescale Semiconductor.
The MPC86xADS is meant to serve as a platform for s/w and h/w
development around the MPC86X processor families.

MPC885ADS

MPC885ADS

Freescale Semiconductor MPC885 Application Development System (ADS).
Also known as DUET.
The MPC885ADS is meant to serve as a platform for s/w and h/w
development around the MPC885 processor family.

PPC_EP88XC

Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)

This enables support for the Embedded Planet EP88xC board.

This board is also resold by Freescale as the QUICCStart
MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.

PPC_ADDER875

Analogue & Micro Adder 875

This enables support for the Analogue & Micro Adder 875
board.

TQM8XX

TQM8XX

support for the mpc8xx based boards from TQM.

Menu: Freescale Ethernet driver platform-specific options

MPC8xx_SECOND_ETH

Second Ethernet channel

This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
The latter will use SCC1, for 885ADS you can select it below.

choice
prompt "Second Ethernet channel"
depends on MPC8xx_SECOND_ETH
default MPC8xx_SECOND_ETH_FEC2

config MPC8xx_SECOND_ETH_FEC2
bool "FEC2"
depends on MPC885ADS
help
Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
(often 2-nd UART) will not work if this is enabled.

config MPC8xx_SECOND_ETH_SCC3
bool "SCC3"
depends on MPC885ADS
help
Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
(often 1-nd UART) will not work if this is enabled.

endchoice

Menu: MPC8xx CPM Options

Generic MPC8xx Options

8xx_GPIO

GPIO API Support

Saying Y here will cause the ports on an MPC8xx processor to be used
with the GPIO API.  If you say N here, the kernel needs less memory.

If in doubt, say Y here.

8xx_CPU15

CPU15 Silicon Errata

This enables a workaround for erratum CPU15 on MPC8xx chips.
This bug can cause incorrect code execution under certain
circumstances.  This workaround adds some overhead (a TLB miss
every time execution crosses a page boundary), and you may wish
to disable it if you have worked around the bug in the compiler
(by not placing conditional branches or branches to LR or CTR
in the last word of a page, with a target of the last cache
line in the next page), or if you have used some other
workaround.

If in doubt, say Y here.

8xx_CPU15

Microcode patch selection

Help not implemented yet, coming soon.

USB_SOF_UCODE_PATCH

USB SOF patch

Help not implemented yet, coming soon.

I2C_SPI_UCODE_PATCH

I2C/SPI relocation patch

Help not implemented yet, coming soon.

I2C_SPI_SMC1_UCODE_PATCH

I2C/SPI/SMC1 relocation patch

Help not implemented yet, coming soon.

SMC_UCODE_PATCH

SMC relocation patch

This microcode relocates SMC1 and SMC2 parameter RAMs at
offset 0x1ec0 and 0x1fc0 to allow extended parameter RAM
for SCC3 and SCC4.

Menu: 8xx advanced setup

PIN_TLB

Pinned Kernel TLBs

On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
table 4 TLBs can be pinned.

It reduces the amount of usable TLBs to 28 (ie by 12%). That's the
reason why we make it selectable.

This option does nothing, it just activate the selection of what
to pin.

PIN_TLB_DATA

Pinned TLB for DATA

This pins the first 32 Mbytes of memory with 8M pages.

PIN_TLB_IMMR

Pinned TLB for IMMR

This pins the IMMR area with a 512kbytes page. In case
CONFIG_PIN_TLB_DATA is also selected, it will reduce
CONFIG_PIN_TLB_DATA to 24 Mbytes.