OR1K_1200

OR1200

Generic OpenRISC 1200 architecture

DCACHE_WRITETHROUGH

Have write through data caches

Select this if your implementation features write through data caches.
Selecting 'N' here will allow the kernel to force flushing of data
caches at relevant times. Most OpenRISC implementations support write-
through data caches.

If unsure say N here

Menu: Class II Instructions

OPENRISC_HAVE_INST_FF1

Have instruction l.ff1

Select this if your implementation has the Class II instruction l.ff1

OPENRISC_HAVE_INST_FL1

Have instruction l.fl1

Select this if your implementation has the Class II instruction l.fl1

OPENRISC_HAVE_INST_MUL

Have instruction l.mul for hardware multiply

Select this if your implementation has a hardware multiply instruction

OPENRISC_HAVE_INST_DIV

Have instruction l.div for hardware divide

Select this if your implementation has a hardware divide instruction

SMP

Symmetric Multi-Processing support

This enables support for systems with more than one CPU. If you have
a system with only one CPU, say N. If you have a system with more
than one CPU, say Y.

If you don't know what to do here, say N.

OPENRISC_NO_SPR_SR_DSX

use SPR_SR_DSX software emulation

SPR_SR_DSX bit is status register bit indicating whether
the last exception has happened in delay slot.

OpenRISC architecture makes it optional to have it implemented
in hardware and the OR1200 does not have it.

Say N here if you know that your OpenRISC processor has
SPR_SR_DSX bit implemented. Say Y if you are unsure.

OPENRISC_HAVE_SHADOW_GPRS

Support for shadow gpr files

Say Y here if your OpenRISC processor features shadowed
register files. They will in such case be used as a
scratch reg storage on exception entry.

On SMP systems, this feature is mandatory.
On a unicore system it's safe to say N here if you are unsure.

CMDLINE

Default kernel command string

On some architectures there is currently no way for the boot loader
to pass arguments to the kernel. For these architectures, you should
supply some command-line options at build time by entering them
here.

Menu: Debugging options

JUMP_UPON_UNHANDLED_EXCEPTION

Try to die gracefully

Now this puts kernel into infinite loop after first oops. Till
your kernel crashes this doesn't have any influence.

Say Y if you are unsure.

OPENRISC_ESR_EXCEPTION_BUG_CHECK

Check for possible ESR exception bug

This option enables some checks that might expose some problems
in kernel.

Say N if you are unsure.