NIOS2_MEM_BASE

Memory base address

This is the physical address of the memory that the kernel will run
from. This address is used to link the kernel and setup initial memory
management. You should take the raw memory address without any MMU
or cache bits set.
Please not that this address is used directly so you have to manually
do address translation if it's connected to a bridge.

Device tree

NIOS2_DTB_AT_PHYS_ADDR

DTB at physical address

When enabled you can select a physical address to load the dtb from.
Normally this address is passed by a bootloader such as u-boot but
using this you can use a devicetree without a bootloader.
This way you can store a devicetree in NOR flash or an onchip rom.
Please note that this address is used directly so you have to manually
do address translation if it's connected to a bridge. Also take into
account that when using an MMU you'd have to ad 0xC0000000 to your
address

NIOS2_DTB_PHYS_ADDR

DTB Address

Physical address of a dtb blob.

NIOS2_DTB_SOURCE_BOOL

Compile and link device tree into kernel image

This allows you to specify a dts (device tree source) file
which will be compiled and linked into the kernel image.

NIOS2_DTB_SOURCE

Device tree source file

Absolute path to the device tree source (dts) file describing your
system.

Nios II instructions

NIOS2_ARCH_REVISION

Select Nios II architecture revision

Select between Nios II R1 and Nios II R2 . The architectures
are binary incompatible. Default is R1 .

NIOS2_HW_MUL_SUPPORT

Enable MUL instruction

Set to true if you configured the Nios II to include the MUL
instruction.  This will enable the -mhw-mul compiler flag.

NIOS2_HW_MULX_SUPPORT

Enable MULX instruction

Set to true if you configured the Nios II to include the MULX
instruction.  Enables the -mhw-mulx compiler flag.

NIOS2_HW_DIV_SUPPORT

Enable DIV instruction

Set to true if you configured the Nios II to include the DIV
instruction.  Enables the -mhw-div compiler flag.

NIOS2_BMX_SUPPORT

Enable BMX instructions

Set to true if you configured the Nios II R2 to include
the BMX Bit Manipulation Extension instructions. Enables
the -mbmx compiler flag.

NIOS2_CDX_SUPPORT

Enable CDX instructions

Set to true if you configured the Nios II R2 to include
the CDX Bit Manipulation Extension instructions. Enables
the -mcdx compiler flag.

NIOS2_FPU_SUPPORT

Custom floating point instr support

Enables the -mcustom-fpu-cfg=60-1 compiler flag.

NIOS2_CI_SWAB_SUPPORT

Byteswap custom instruction

Use the byteswap (endian converter) Nios II custom instruction provided
by Altera and which can be enabled in QSYS builder. This accelerates
endian conversions in the kernel (e.g. ntohs).

NIOS2_CI_SWAB_NO

Byteswap custom instruction number

Number of the instruction as configured in QSYS Builder.

Cache settings

CUSTOM_CACHE_SETTINGS

Custom cache settings

This option allows you to tweak the cache settings used during early
boot (where the information from device tree is not yet available).
There should be no reason to change these values. Linux will work
perfectly fine, even if the Nios II is configured with smaller caches.

Say N here unless you know what you are doing.

NIOS2_DCACHE_SIZE

D-Cache size

Maximum possible data cache size.

NIOS2_DCACHE_LINE_SIZE

D-Cache line size

Minimum possible data cache line size.

NIOS2_ICACHE_SIZE

I-Cache size

Maximum possible instruction cache size.