If FPU ISA is used in user space, this configuration shall be Y to enable required support in kernel such as fpu context switch and fpu exception handler. If no FPU ISA is used in user space, say N.
Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can enhance system performance by reducing the context switch frequency of the FPU register. For normal case, say Y.
Say Y here to enable arithmetic of denormalized number. Enabling this feature can enhance the precision for tininess number. However, performance loss in float point calculations is possibly significant due to additional FPU exception. If the calculated tolerance for tininess number is not critical, say N to prevent performance loss.
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3 registers($LB, $LC, $LE) for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers. If unsure, say N.
If this CPU is using VIPT data cache and its cache way size is larger than page size, say Y. If it is using PIPT data cache, say N. If unsure, say Y.
The data cache of N15/D15 is implemented as PIPT and it will not cause the cache aliasing issue. The rest cpus(N13, N10 and D10) are implemented as VIPT data cache. It may cause the cache aliasing issue if its cache way size is larger than page size. You can specify the CPU type directly or choose CPU_V3 if unsure. A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. A kernel built for N15 is able to run on N15 or D15. A kernel built for D10 is able to run on D10 or D15. A kernel built for D15 is able to run on D15. A kernel built for N13 is able to run on N15, N13 or D15.
Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N.
Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N.
Say Y here to use the data cache in writethrough mode. Unless you specifically require this or are unsure, say N.
Say Y here to enable write-back memory with no-write-allocation policy.
Andes processors cannot load/store information which is not naturally aligned on the bus, i.e., a 4 byte load must start at an address divisible by 4. On 32-bit Andes processors, these non-aligned load/store instructions will be emulated in software if you say Y here, which has a severe performance impact. With an IP-only configuration it is safe to say N, otherwise say Y.
Andes processors load/store world/half-word instructions can access unaligned memory locations without generating the Data Alignment Check exceptions. With an IP-only configuration it is safe to say N, otherwise say Y.
The address space of Andes processors is only 4 Gigabytes large and it has to accommodate user address space, kernel address space as well as some memory mapped IO. That means that, if you have a large amount of physical memory and/or IO, not all of the memory can be "permanently mapped" by the kernel. The physical memory that is not permanently mapped is called "high memory". Depending on the selected kernel/user memory split, minimum vmalloc space and actual amount of RAM, you may not need this option which should result in a slightly faster kernel. If unsure, say N.
Say Y here to enable L2 cache if your SoC are integrated with L2CC. If unsure, say N.
Say Y here to enable hardware prefetcher feature. Only when CPU_VER.REV >= 0x09 can support.
Select the desired split between kernel and user memory. If you are not absolutely sure what you are doing, leave this option alone! config VMSPLIT_3G bool "3G/1G user/kernel split" config VMSPLIT_3G_OPT bool "3G/1G user/kernel split (for full 1G low memory)" config VMSPLIT_2G bool "2G/2G user/kernel split" config VMSPLIT_1G bool "1G/3G user/kernel split"