The CN63XXP1 chip requires build time workarounds to function reliably, select this option to enable them. These workarounds will cause a slight decrease in performance on non-CN63XXP1 hardware, so it is recommended to select "n" unless it is known the workarounds are needed.
CVMSEG LM is a segment that accesses portions of the dcache as a local memory; the larger CVMSEG is, the smaller the cache is. This selects the size of CVMSEG LM, which is in cache blocks. The legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is between zero and 6192 bytes).
Enable locking parts of the kernel into the L2 cache.
Lock the low level TLB fast path into L2.
Lock the low level exception handler into L2.
Lock the low level interrupt handler into L2.
Lock the 2nd level interrupt handler in L2.
Lock the kernel's implementation of memcpy() into L2.
This driver is a module to measure interrupt latency using the the CIU Timers on Octeon. To compile this driver as a module, choose M here. The module will be called octeon-ilm