The original ARC ISA of ARC600/700 cores
ISA for the Next Generation ARC-HS cores
Support for ARC750 core
Support for ARC770 core introduced with Rel 4.10 (Summer 2011) This core has a bunch of cool new features: -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) Shared Address Spaces (for sharing TLB entries in MMU) -Caches: New Prog Model, Region Flush -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
Support for ARC HS38x Cores based on ARCv2 ISA The notable features are: - SMP configurations of up to 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU...
Override default -mcpu=xxx compiler flag (which is set depending on the ISA version) with the specified value. NOTE: If specified flag isn't supported by current compiler the ISA default value will be used as a fallback.
Build kernel for Big Endian Mode of ARC CPU
This enables support for systems with more than one CPU.
In SMP configuration cores can be configured as Halt-on-reset or they could all start at same time. For Halt-on-reset, non masters are parked until Master kicks them so they can start off at designated entry point. For other case, all jump to common entry point and spin wait for Master's signal.
This IP block enables SMP in ARC-HS38 cores. It provides for cross-core interrupts, multi-core debug hardware semaphores, shared memory,....
Starting with ARC700 4.9, Cache line length is configurable, This option specifies "N", with Line-len = 2 power N So line lengths of 32, 64, 128 are specified by 5,6,7, respectively Linux only supports same line lengths for I and D caches.
This can be used to over-ride the global I/D Cache Enable on a per-page basis (but only for pages accessed via MMU such as Kernel Virtual address or User Virtual Address) TLB entries have a per-page Cache Enable Bit. Note that Global I/D ENABLE + Per Page DISABLE works but corollary Global DISABLE + Per Page ENABLE won't work
Single Cycle RAMS to store Fast Path Code
Single Cycle RAMS to store Fast Path Data
Orig ARC700 MMU
Fixed the deficiency of v1 - possible thrashing in memcpy scenario when 2 D-TLB and 1 I-TLB entries index into same 2way set.
Introduced with ARC700 4.10: New Features Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) Shared Address Spaces (SASID)
Choose between 8k vs 16k
Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory zones.
ARCompact FPU has internal registers to assist with Double precision Floating Point operations. There are control and stauts registers for floating point exceptions and rounding modes. These are preserved across task context switch when enabled.
The ARC HS architecture supports unaligned memory access which is disabled by default. Enable unaligned access in hardware and use software to use it
Enable gcc to generate 64-bit load/store instructions ISA mandates even/odd registers to allow encoding of two dest operands with 2 possible source operands. default y
Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process
Depending on the configuration, CPU can contain DSP registers (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). Bellow is options describing how to handle these registers in interrupt entry / exit and in context switch.
No DSP extension presence in HW
DSP extension presence in HW, no support for DSP-enabled userspace applications. We don't save / restore DSP registers and only do some minimal preparations so userspace won't be able to break kernel
DSP extension presence in HW, support save / restore DSP registers to run DSP-enabled userspace applications
DSP and AGU extensions presence in HW, support save / restore DSP and AGU registers to run DSP-enabled userspace applications
On HS cores, taken interrupt auto saves the regfile on stack. This is programmable and can be optionally disabled in which case software INTERRUPT_PROLOGUE/EPILGUE do the needed work
On HS cores, loop buffer (LPB) is programmable in runtime and can be optionally disabled.
ARC700 divides the 32 bit phy address space into two equal halves -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel Typically Linux kernel is linked at the start of untransalted addr, hence the default value of 0x8zs. However some customers have peripherals mapped at this addr, so Linux needs to be scooted a bit. If you don't know what the above means, leave this setting alone. This needs to match memory start address specified in Device Tree
By default Linux is linked at base of RAM. However in some special cases (such as HSDK), Linux can't be linked at start of DDR, hence this option.
With ARC 2G:2G address split, only upper 2G is directly addressable by kernel. Enable this to potentially allow access to rest of 2G and PAE in future
Enable access to physical memory beyond 4G, only supported on ARC cores with 40 bit Physical Addressing support
The kernel address space is carved out of 256MB of translated address space for catering to vmalloc, modules, pkmap, fixmap. This however may not suffice vmalloc requirements of a 4K CPU EZChip system. So allow this to be stretched to 512 MB (by extending into the reserved kernel-user gutter)
This reserved Register R25 to point to Current Task in kernel mode. This saves memory access for each such access
This enables misaligned 16 & 32 bit memory access from user space. Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide potential bugs in code
This options allows a Linux userland apps to directly access host file system (open/creat/read/write etc) with help from Metaware Debugger. This can come in handy for Linux-host communication when there is no real usable peripheral such as EMAC.
Compiles the kernel with DWARF unwind information and can be used to get stack backtraces. If you say Y here the resulting kernel image will be slightly larger but not slower, and it will give very useful debugging information. If you don't debug the kernel, you can say N, but we may not be able to solve problems without frame unwind information
Enable paranoid checks and self-test of both ARC-specific and generic part of static keys (jump labels) related code.
Set the name of the DTB to embed in the vmlinux binary Leaving it blank selects the minimal "skeleton" dtb