# HG changeset patch
# User Rob Landley <rob@landley.net>
# Date 1179383897 14400
# Node ID 07d8795fc19cb3cf7aa7472760c43b5649e2f0f4
# Parent  a0678c2ae9b8f82f168976c6bc46ed21a3f3ce89
Link to ars technica paedia broke because ars is now using Windows 2003 on
its' webserver and can't competently show "index.html" for a directory.  Wheee.

diff -r a0678c2ae9b8 -r 07d8795fc19c www/design.html
--- a/www/design.html	Mon Apr 30 00:08:48 2007 -0400
+++ b/www/design.html	Thu May 17 02:38:17 2007 -0400
@@ -55,7 +55,7 @@
 cacheing</a>, and this one on 
 <a href=http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars>bandwidth
 and latency</a>.
-And there's <a href=http://arstechnica.com/paedia/>more where that came from</a>.)
+And there's <a href=http://arstechnica.com/paedia/index.html>more where that came from</a>.)
 Running out of L1 cache can execute one instruction per clock cycle, going
 to L2 cache costs a dozen or so clock cycles, and waiting for a worst case dram
 fetch (round trip latency with a bank switch) can cost thousands of