annotate www/architectures.html @ 1727:45c936d93711 draft

Drop ROOT_NODIRS, it's not worth the complexity to support both layouts.
author Rob Landley <rob@landley.net>
date Sun, 11 Jan 2015 12:01:30 -0600
parents e50c2b9588b8
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1 <html>
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2 <title>Target architectures</title>
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3 <body>
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4
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5 <!--#include file="header.html" -->
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7 <p>Thumbnail oversimplification of processors:</p>
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9 <ul>
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10 <li>
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11 <h1>What processors does Aboriginal Linux currently support?</h1>
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12 <ul>
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13 <li><a href=#arm>ARM</a></li>
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14 <li><a href=#m68k>Motorola 68000</a></li>
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15 <li><a href=#mips>Mips</a></li>
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16 <li><a href=#ppc>PowerPC</a></li>
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17 <li><a href=#sh4>SH4</a></li>
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18 <li><a href=#sparc>Sparc</a></li>
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19 <li><a href=#x86>x86</a></li>
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20 </ul>
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21 <li><p><a href=#when>What processors are supported by Linux, and when was support added for each one?</a></p></li>
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22
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23 <li><p><a href=#where>Where did all these processors come from?</a></p>
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24 <ul>
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25 <li><b>Before Linux</b></li>
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26 <li><b>32 bits and RISC</b></li>
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27 <li><b>Mobile processors</b></li>
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28 </ul>
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29 </ul>
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31 <hr /><h1><a name="arm" \><center>ARM</center></h1>
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32
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33 <p>The ARM processor is popular in the embedded space because it has the best
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34 power consumption to performance ratio, meaning it has the longest battery
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35 life and smallest amount of heat generated for a given computing task.
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36 It's the standard processor of smartphones. The 64 bit version (ARMv8)
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37 was announced in 2011 with a 2014 ship date for volume silicon.</p>
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38
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39 <h2>Processor vs architecture</h2>
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40
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41 <p>Although ARM hardware has many different processor designs with varying
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42 clock speeds, cache sizes, and integrated peripherals, from a software
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43 perspective what matters is ARM
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44 <a href=http://www.arm.com/products/CPUs/architecture.html>architectures</a>, which are the different
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45 instruction sets a compiler can produce. The architecture names have a "v"
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46 in them and the processor designs don't, so "ARM922T" is a hardware processor
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47 design which implements the "ARMv4T" software instruction set.</p>
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48
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49 <p>The basic architectures are numbered: ARMv3, ARMv4, ARMv5, ARMv6, and
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50 ARMv7. An ARMv5 capable processor can run ARMv4 binaries, ARMv6 can run ARMv5,
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51 and so on. Each new architecture is a superset of the old ones, and the main
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52 reason to compile for newer platforms is efficiency: faster speed and better
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53 battery life. (I.E. they work about like i386, i486, i586, and i686 do in
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54 the x86 world. Recompiling ARMv4 code to ARMv5 code provides about a 25%
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55 speedup on the same hardware.)</p>
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56
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57 <p>The oldest architecture this compatibility goes back to is ARMv3 (which
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58 introduced 32-bit addressing), but that hardware is now obsolete. (Not just no
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59 longer being sold, but mostly cycled out of the installed base.) The oldest
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60 architecture still in use is "ARMv4", which should run on any ARM hardware
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61 still in use today (except ARMv7M, which is ARM in name only: it only
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62 implements the Thumb2 instruction set, not traditional arm instructions).</p>
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63
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64 <h2>Architecture extensions</h2>
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65
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66 <p>ARM architectures can have several instruction set extensions, indicated
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67 by letters after the ARMv# part. Some (such as the letter "E" denoting the
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68 "Jazelle" bytecode interpreter, which provides hardware acceleration for
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69 running Java bytecode) can safely be ignored if you're not using them, and
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70 others are essentially always there in certain architectures (such as the DSP
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71 extension signified by the letter "E" which always seems to be present in
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72 ARMv5). But some are worth mentioning:</p>
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73
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74 <p>The "Thumb" extension (ARMv4T) adds
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75 a smaller instruction set capable of fitting more code in a given amount
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76 of memory. Unfortunately thumb instructions often run more slowly, and
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77 the instruction set isn't complete enough to implement a kernel, so they
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78 supplement rather than replace the conventional ARM instruction set. Note
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79 that all ARMv5 and later processors include Thumb support by default, only
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80 ARMv4T offers it as an extension. The newer "Thumb2" version fixes most of the
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81 deficiencies of the original Thumb instruction set (you _can_ do a kernel
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82 in that), and is part of the ARMv7 architecture. The ARMv7M (Mangled? Mutant?)
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83 chip supports nothing _but_ Thumb2, abandoning backwards compatability with
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84 any other ARM binaries.</p>
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85
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86 <p>The VFP (Vector Floating Point) coprocessor provides hardware floating
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87 point acceleration. There are some older hardware floating point options,
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88 and some newer ones backwards compatible with VFP, but in general you can
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89 treat a chip as either "software floating point" or "VFP".</p>
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90
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91 <p>The other detail is "l" vs "b" for little-endian and big-endian.
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92 In theory ARM can do both (this is a compiler distinction, not a hardware
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93 distinction), but in practice little-endian is almost universally
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94 used on ARM, and most boards are wired up to support little-endian only even if
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95 the processor itself can theoretically handle both.</p>
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96
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97 <p>So for example, "armv4tl" is ARMv4 with Thumb extensions, little endian.
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98 This is the minimum requirements to use EABI, the current binary interface
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99 standard for Arm executables. (The older OABI is considered obsolete.)</p>
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100
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101 <h2>Application Binary Interface</h2>
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102
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103 <p>Linux initially implemented a somewhat ad-hoc ABI for ARM with
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104 <a href=http://www.linuxfordevices.com/c/a/Linux-For-Devices-Articles/Why-ARMs-EABI-matters/>poor
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105 performance and several limitations</a>, and when ARM got around to documenting
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106 a new one the main downside was that it was incompatible with the old
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107 binaries.</p>
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108
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109 <p>So ARM has two ABIs that can run on the same hardware, the old one is
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110 called OABI and the new one is
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111 <a href=http://wiki.debian.org/ArmEabiPort>EABI</a>. (This is a bit like
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112 the way BSD binaries won't run under Linux even though the hardware's the
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113 same, or the long ago switch from
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114 <a href=http://www.linuxjournal.com/article/1059>aout to ELF</a> executable
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115 formats.</p>
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116
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117 <p>The oldest hardware that can run EABI is ARMv4T, so ARMv4 hardware
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118 without the Thumb extensions still has to use OABI, which is why you don't
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119 see much of that anymore. The kernel, C
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120 library, and compiler must all agree which ABI is in use or the binaries
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121 won't run. The transition to EABI happened somewhere around 2005, and
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122 these days everything is EABI.</p>
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123
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124 <h2>Further Reading</h2>
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125
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126 <p>In theory the best reference for ARM processors is the
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127 <a href=http://www.arm.com>website of ARM Limited</a>, but unfortunately
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128 they make it somewhat hard to find information about their
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129 <a href=http://www.arm.com/products/CPUs/ARM920T.html>older products</a>
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130 and <a href=http://www.arm.com/products/CPUs/families/ARM7Family.html>many
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131 of their pages</a> are more concerned with advertising their newest products
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132 than giving the requested information. Wikipedia may be less frustrating,
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133 and occasionally even accurate.</p>
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134
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135 <hr /><h1><a name="m68k" \><center>Motorola 68000</center></h2>
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136
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137 <p>Very popular in the 80's, the first widely used 32-bit processor.
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138 It was in the original Apple Macintosh, the first Sun workstations, the
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139 Commodore Amiga, the Atari 800, and so on.</p>
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140
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141 <p>Still trying to get QEMU to support it, the Aranym Atari emulator has
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142 run an Aboriginal M68k chroot but requires a different kernel config.
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143 In theory the q800 branch of git://gitorious.org/qemu-m68k/qemu-m68k is
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144 working on support for the last m68k macintosh model (supporting 256 megs
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145 of ram), but in practice it doesn't boot Linux yet.</p>
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146
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147 <p>Coldfire is a nommu variant used in early handhelds.</p>
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148
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149 <hr /><h1><a name="mips" \><center>Mips</center></h1>
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150
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151 <p>In the 1970's MIPS was a common acronym for "Millions of Instructions
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152 Per Second", a measure of processor speed. It also sounded like MITS
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153 (Microcontroller Instrumentation and Telemetry Systems), the company that
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154 made the first microcomputer (the MITS Altair).</p>
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155
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156 <p>In 1981 a RISC architecture
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157 design team at Stanford University led by John L. Hennessy (who went on
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158 to become president of the university) designed a
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159 "Microprocessor without Interlocked Pipeline Stages", and used that as an
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160 excuse to turn the acronym into a
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161 <a href="http://www.mips.com/media/files/mips_trademark.pdf">registered
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162 trademark</A> of Mips Technologies, inc.</p>
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163
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164 <p>Mips used to be neck and neck with ARM until the company behind Mips
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165 fought a <a href=http://landley.net/notes-2009.html#14-12-2009>legal
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166 battle with Lexra</a> that turned off enough customers to allow ARM to pull
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167 ahead and become the standard processor of smartphones. The mips platform
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168 has never fully recovered, but retains some niches, most prominently in
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169 devices connected to wall current (routers, set top boxes, etc).
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170 One advantage Mips historically had over Arm was availability of an FPGA
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171 version which allowed easier System-On-Chip prototyping. (This was before
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172 Linux ran on the Xylinx Microblaze.)</p>
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173
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174 <p>The glory days of Mips were when Silicon Graphics built unix graphics
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175 workstations around it. (SGI created the first 3D accelerator card, for
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176 the DEC VAX minicomputer. When Voodoo cards brought 3D to PCs, SGI bought
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177 half of Cray and tried to go upmarket into supercomputers, hired an
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178 ex-microsoft executive to be CEO who conviced them to abandon unix and
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179 port everything to Windows NT before returning to Microsoft, then they
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180 jumped on the Itanic bandwagon. Long story short: they don't do Mips
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181 anymore.) SGI's workstation success contributed to some game consoles
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182 such as the (Playstation 2) being mips based.</p>
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183
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184 <p>The company's website talks about <a href=http://www.mips.com/customers/licensees/>their customers</a>.</p>
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185
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186 <hr /><h1><a name="ppc" \><center>PowerPC</center></h1>
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187
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188 <p>Apple's original Macintosh computers used Motorola 68000 processors.
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189 After Steve Jobs left to create NeXT and Pixar, "Project Pink" (an alliance
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190 between Apple, Motorola, and IBM) took IBM's "POWER" minicomputer processor
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191 and scaled it down for use in macintoshes. This created a "PC version of the
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192 POWER architecture", called PowerPC. (This lasted about a decade before
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193 Jobs returned and switched new Macs to x86, and did Arm-based phones and
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194 tablets.)</p>
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195
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196 <p>Motorola tried to strip PPC down for use in smartphones (creating the 880,
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197 a chip implementing a subset of the ppc instruction set), but
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198 that ended when they spun off their processor division as a new company
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199 (Freescale) and switched their phones to arm chips from other vendors.
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200 IBM tried to strip down its own embedded version (the 440) selecting a
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201 different (incompatible) subset of the powerpc instruction set. QEMU's
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202 "bamboo" board emulates this, and userspace 440 code should run on a full
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203 PPC (the kernel might not, the MMU implementation's different).</p>
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204
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205 <p>Powerpc is still around in game consoles (Xbox, Xbox360, Playstation 3)
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206 and some supercomputers.
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207 These days the power architecture is maintained by <a href=http://power.org>a
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208 consortium.</a>
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209
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210 <hr /><h1><a name="sh4" \><center>SuperH</center></h1>
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211
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212 <p>Japan's first major homegrown 32-bit processor architecture was widely
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213 used in the automotive industry, and wound up in the dreamcast gaming
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214 console. Often called "sh4", because although there were sh versions 1 through
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215 3 they didn't really make it out of Japan.</p>
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216
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217 <p>Although sh4 is reasonably well supported by QEMU, Hitachi spun this
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218 processor design off into a seprate company called Renesas, which ranges
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219 from "confused" to "actively hostile" at the idea that anyone who isn't already
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220 a paying customer might be interested in this processor.</p>
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221
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222 <hr /><h1><a name="sparc" \><center>Sparc</center></h1>
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223
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224 <p>Created by Sun Microsystems as a replacement for the m68k, and mostly
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225 used in-house by them until they went out of business. (Fujitsu made some
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226 supercomputers with it, during the same period Alpha and iTanic were used in
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227 that space.) Oracle bought Sun's corpse, but according to James Gosling
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228 (creator of the Java programming language), they were more interested in
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229 the lawsuit potential than the technology.</p>
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230
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231 <hr /><h1><a name="x86" \><center>x86</center></h1>
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232
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233 <p>The standard PC architecture, in 32-bit and 64-bit flavors.</p>
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234
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235 <p>The reason the x86 directory in Linux is newer than some other architectures
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236 is the 32-bit and 64-bit directories were merged together, and the date of
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237 the oldest commit in the directory is the merge. In reality, i386 was the
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238 original Linux architecture back in 1991.</p>
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239
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240 <hr>
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241
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242 <a name="when">
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243 <h1>What processors are supported by Linux, and when was support added
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244 for each one?</h1>
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245
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246 <p>We can actually beat this information out of the <a href=http://landley.net/kdocs/fullhist>linux-fullhist</a> git repository, by doing:</p>
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247 <blockquote><p>
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248 cd arch && for i in *; do echo -en "$i\t" && git log $i | sed -n 's/^Date:[ \t]*//p' | tail -n 1 | awk '{print $2" "$3" "$5}'; done
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249 </p></blockquote>
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250
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251 <p>Removing "Kconfig" and "um" (user mode linux, not a processor type),
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252 as of the 3.9 kernel this gives us:</p>
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253
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254 <table>
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255 <tr><td>alpha</td><td>Nov 27 1994</td></tr>
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256 <tr><td>sparc</td><td>Dec 4 1994</td></tr>
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257 <tr><td>mips</td><td>Jan 12 1995</td></tr>
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258 <tr><td>m68k</td><td>Mar 7 1996</td></tr>
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259 <tr><td>arm</td><td>Jan 20 1998</td></tr>
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260 <tr><td>sh</td><td>Jun 30 1999</td></tr>
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261 <tr><td>ia64</td><td>Jan 4 2000</td></tr>
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262 <tr><td>s390</td><td>Mar 10 2000</td></tr>
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263 <tr><td>parisc</td><td>Oct 3 2000</td></tr>
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264 <tr><td>cris</td><td>Jan 30 2001</td></tr>
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265 <tr><td>um</td><td>Sep 11 2002</td></tr>
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266 <tr><td>h8300</td><td>Apr 17 2003</td></tr>
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267 <tr><td>m32r</td><td>Sep 16 2004</td></tr>
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268 <tr><td>frv</td><td>Jan 4 2005</td></tr>
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269 <tr><td>xtensa</td><td>Jun 23 2005</td></tr>
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270 <tr><td>powerpc</td><td>Sep 19 2005</td></tr>
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271 <tr><td>avr32</td><td>Sep 25 2006</td></tr>
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272 <tr><td>blackfin</td><td>May 6 2007</td></tr>
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273 <tr><td>x86</td><td>Oct 11 2007</td></tr>
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274 <tr><td>mn10300</td><td>Feb 8 2008</td></tr>
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275 <tr><td>microblaze</td><td>Mar 27 2009</td></tr>
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276 <tr><td>score</td><td>Jun 12 2009</td></tr>
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277 <tr><td>tile</td><td>May 28 2010</td></tr>
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278 <tr><td>unicore32</td><td>Feb 26 2011</td></tr>
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279 <tr><td>openrisc</td><td>Jun 4 2011</td></tr>
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280 <tr><td>c6x</td><td>Oct 4 2011</td></tr>
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281 <tr><td>hexagon</td><td>Oct 31 2011</td></tr>
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282 <tr><td>arm64</td><td>Mar 5 2012</td></tr>
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283 <tr><td>metag</td><td>Dec 5 2012</td></tr>
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284 <tr><td>arc</td><td>Jan 18 2013</td></tr>
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Rob Landley <rob@landley.net>
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285 </table>
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286
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Rob Landley <rob@landley.net>
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287 <p>This doesn't quite tell the full story: the x86 and powerpc directories
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288 were created by merging together 32 bit and 64 bit versions of the same
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289 architectures: the i386 and x86_64 directories for x86, and the ppc and ppc64
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290 directories for powerpc. (A similar merge of arm and arm64 is expected when
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291 ARMv8 support stabilizes.)</p>
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292
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293 <p>The resulting dates are when the merge happened,
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294 the corresponding architectures were added much earlier.</p>
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295
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296 <a name="where">
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297 <h1>Where did all these processors come from?</h1>
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298
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299 <b>Before Linux</b>
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300
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301 <p>In the 1950's and 60's
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302 <a href=http://landley.net/history/mirror/interviews/olsen.html>mainframe
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303 and minicomputer</a> processors took up an entire circuit board. Unix
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304 started on these kind of systems, few of them remain in use today.</p>
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305
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Rob Landley <rob@landley.net>
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306 <p>In 1969 an <a href=http://landley.net/history/mirror/intel/Hoff.html>engineer
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307 at Intel</a> invented the first microprocessor, the Intel 4004, by being the
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308 first to squeeze all the functions of a CPU onto a single silicon "chip".
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309 As <a href=http://www.fool.com/CashKing/1998/CashKingPort980421.htm>transistor</a>
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310 <a href=http://www.fool.com/CashKing/1998/CashKingPort980422.htm>budgets</a>
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311 <a href=http://www.fool.com/CashKing/1998/CashKingPort980421.htm>increased</a>
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312 they upgraded the 4004's design into the 8008 and then the 8080, the chip
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313 inside coin-operated Space Invaders machines and the Mits Altair. The Altair
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314 was widely cloned to form the first family of microcomputers, which contained
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315 (and were named after) the S-100 bus, programed in Basic from
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316 a startup called Micro-soft, and ran an OS called
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317 <a href=http://landley.net/history/mirror/cpm/history.html>CP/M</a>
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318 from a startup called Digital Research.</p>
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319
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320 <p><a href=http://landley.net/history/mirror/interviews/Faggin.html>One of the
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321 Intel engineers</a> left to form his own company that made an 8080
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322 clone called the Z80. But the main alternative to the 8080 was from
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323 some ex-motorola engineers who left form MOStek, the company
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324 that did the (much cheaper) 6502 processor, with its own instruction
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325 set. Motorola sued the escaped engineers for being better at it than they were,
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326 and in the end the engineers went back to Motorola and
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327 commodore bought the rest of the company to use these processors in the Vic 20
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328 (the first computer to sell a million units) and its successor the Commodore
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329 64 (even more popular). The 6502 also wound up running the Apple I and Apple II,
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330 and the first big home game console (the Atari 2600).</p>
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331
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332 <p>The march of Moore's Law quickly drove the microcomputer world to
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333 <a href=http://www.catb.org/~esr/writings/world-domination/world-domination-201.html>move beyond 8 bit processors</a>. Moore's Law says that memory size doubles
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334 every 18 months, which quickly became a self-fulfulling prophecy hardware
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335 manufacturers used to manage inventory and schedule product releases.</p>
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336
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337 <p>The first widely cloned microcomputer (the MITS Altair) was introduced in
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338 1975, and by the middle of the year established a range of 1-4 kilobytes of
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339 memory installed in altair compatible systems. (The original Altairs
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340 had only 256 bytes memory, but that wasn't enough and 1k expansion boards
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341 immediately became standard equipment. The first version of its standard
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342 de-facto standard programming language, Micro-soft basic, required 7k of
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343 memory to run but that was too expensive so they trimmed it down to run in
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344 4k.) From then on Moore's Law turned the old high end into the new low end
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345 every 3 years. (In 1978: 4-16k. In 1981, 16-64k.)</p>
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346
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347 <p>These early microcomputers were called 8-bit machines because they had
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348 8-bit registers, storing values from 0 to 255. But they used pairs of registers
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349 to access memory, providing 16 bits (64k) of address space. That was enough for
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350 four 18-month Moore's Law doublings before the high end of the microcomputer
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351 address range hit the 64k address space limit in mid-1981.</p>
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Rob Landley <rob@landley.net>
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352
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Rob Landley <rob@landley.net>
parents: 1595
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353 <p>The result was a switch to 16-bit systems. IBM introduced its PC in
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Rob Landley <rob@landley.net>
parents: 1595
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354 August 1981, based on Intel's 8086 processor (actually a variant called
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
355 the 8088 that ran the same software but fit in cheaper 8-bit motherboards
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Rob Landley <rob@landley.net>
parents: 1595
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356 and took twice as many clock cycles to do anything). True to form, it
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Rob Landley <rob@landley.net>
parents: 1595
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357 offered anywhere from 16k to 64k of memory preinstalled.</p>
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Rob Landley <rob@landley.net>
parents: 1595
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358
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Rob Landley <rob@landley.net>
parents: 1595
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359 <p>The main competitor to the 8086 was Motorola's 32-bit 68000 line of
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Rob Landley <rob@landley.net>
parents: 1595
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360 processors, used in just about everything except the PC (Macintosh, Amiga,
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
361 Sun workstations...) Just as the Intel's 8086 was a sequel to the 8080,
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Rob Landley <rob@landley.net>
parents: 1595
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362 the Motorola's 68k was a sequel to the 6502.</p>
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
363
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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364 <p>Motorola skipped 16 bit registers and jumped straight to 32 bits, but back
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Rob Landley <rob@landley.net>
parents: 1595
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365 when 64k was as much memory as most high-end users could afford (costing
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
366 hundreds of dollars) this provided no immediate market advantage. The 68k
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Rob Landley <rob@landley.net>
parents: 1595
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367 powered Apple's Macintosh (and several incompatible designs such as Commodore's
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Rob Landley <rob@landley.net>
parents: 1595
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368 Amiga and Sun's original unix workstations). But Apple successfully defended
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Rob Landley <rob@landley.net>
parents: 1595
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369 its hardware design in court, while IBM lost its court case
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Rob Landley <rob@landley.net>
parents: 1595
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370 against Compaq, spawning an army of clones that quickly marginalized the
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Rob Landley <rob@landley.net>
parents: 1595
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371 proprietary hardware designs and rendered the PC the standard computer.</p>
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Rob Landley <rob@landley.net>
parents: 1595
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372
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
373 <p>The 8086 also used pairs of registers to access memory, but it overlapped
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Rob Landley <rob@landley.net>
parents: 1595
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374 their address ranges so instead of 16+16=32 bits of address space, each
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
375 "segment" started only 16 bits from the previous one (with a 64k offset that
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Rob Landley <rob@landley.net>
parents: 1595
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376 mostly redundantly accessed the same memory as other segments), providing
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Rob Landley <rob@landley.net>
parents: 1595
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377 16+4=20 bits of address space, for 1 megabyte. (The 640k limit of DOS was
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Rob Landley <rob@landley.net>
parents: 1595
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378 because the top third of the address range was reserved for I/O memory,
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Rob Landley <rob@landley.net>
parents: 1595
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379 starting with the video card's frame buffer.)</p>
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Rob Landley <rob@landley.net>
parents: 1595
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380
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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381 <p>The continuing advance of Moore's Law meant high-end PCs would collide
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Rob Landley <rob@landley.net>
parents: 1595
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382 with the 1 megabyte limit in 1987. To prepare for this, Intel introduced its
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Rob Landley <rob@landley.net>
parents: 1595
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383 own 32-bit processor, the 80386, in 1985. Unfortunately IBM had bought the
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Rob Landley <rob@landley.net>
parents: 1595
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384 entire first year's production run of Intel's previous processor (the 80286)
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Rob Landley <rob@landley.net>
parents: 1595
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385 to keep it out of the hands of the PC cloners, and Moore's Law quickly left
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
386 IBM with a giant unsold pile of slow expensive processors. This delayed
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
387 its introduction of new 32-bit PCs until the original cloner introduced
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Rob Landley <rob@landley.net>
parents: 1595
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388 the "Compaq Deskpro 386" and the rest of the clones followed that, leaving
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Rob Landley <rob@landley.net>
parents: 1595
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389 IBM's PCs in obscurity.</p>
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Rob Landley <rob@landley.net>
parents: 1595
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390
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Rob Landley <rob@landley.net>
parents: 1595
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391 <b>32 bits and RISC</b>
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Rob Landley <rob@landley.net>
parents: 1595
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392
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
393 <p>In the 1980's and 90's, a
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Rob Landley <rob@landley.net>
parents: 1595
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394 <a href=http://www.fool.com/portfolios/rulemaker/2000/rulemaker000224.htm>new
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Rob Landley <rob@landley.net>
parents: 1595
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395 technology called RISC</a> led to a gold rush
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
396 of processors hoping to take market share away from Intel. These risc designs
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
397 came from three sources: start-up companies producing new RISC processors,
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
398 surviving mainframe and minicomputer vendors redesigning their big iron to use
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
399 microprocessors, and m68k users giving up on that design once Intel's move
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
400 to 32 bits removed the only argument in its favor. (If m68k had lost out to
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
401 16 bit x86, clearly it was even less interesting after the 386 came out.)</p>
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Rob Landley <rob@landley.net>
parents: 1595
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402
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
403 <p>RISC designs ("Reduced Instruction Set Computers") simplified processor
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
404 instruction sets down to fixed-length instructions that only took one clock
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
405 cycle. This led to more verbose machine code which took up more memory, but
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
406 also meant that since you didn't have to execute the previous instruction
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
407 to figure out where the next one started (because they're all the same size),
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
408 processors could contain a second "execution core" looking over the shoulder
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
409 of the first core to potentially execute the next instruction in the same
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
410 clock cycle (if it didn't use the same registers, memory locations, or depend
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
411 on processor flags set by the previous instruction). Once compilers
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
412 advanced to produce instructions in non-interfering pairs, RISC processors
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
413 added a third core to potentially execute a third instruction in the same
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
414 clock cycle (if that one didn't interfere with the first two).</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
415
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
416 <p>Several processor manufacturers were convinced that RISC designs were
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
417 superior to the older designs (which they called "CISC", for Complex
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
418 Instruction Set Computers). The commodity PC had taken over the market,
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
419 running a large installed base of CISC software, but the cloners were
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
420 sure that during the 16 to 32 bit transition they could capture the market
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
421 when everyone had to throw out their old software anyway.</p>
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
422
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
423 <p>MIPS was one early RISC startup, created and commercialized
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
424 by some university professors based on early RISC research. The ARM design
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
425 came from a tiny start-up in the UK which made the Acorn Risc Machine and
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
426 got a contract with the British Broadcasting Service to sell it as the "BBC
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
427 Micro" in conjunction with BBC educational programming.</p>
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
428
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
429 <p>At the other end of things, IBM engineers produced the Power minicomputer
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
430 architecture, Hewlett Packard developed PA-RISC, Hitachi developed the
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
431 SuperH (more commonly known as sh4), and Digital Equipment
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
432 Corporation migrated its VAX minicomputers to their new Alpha processor
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
433 (the first 64 bit processor).</p>
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
434
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
435 <p>Sun Microsystems develop the Sparc processor to replace m68k, but the
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
436 official successor to m68k came from a partnership between Apple, Motorola,
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
437 and IBM, redesigning IBM's Power processor to produce PowerPC. (Apple's
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
438 macintosh redesign brought its m68k vendor Motorola together with IBM,
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
439 which at the time had the world's leading microchip manufacturing facilities.
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
440 The 90's were a great decade for IBM's microprocessor manufacturing arm: first
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
441 to replace microchips' traditional aluminum wiring with copper, first to layer
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
442 "silicon on insulator" to improve power efficiency, first gigahertz
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
443 processor...)</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
444
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
445 <p>When the PC market smoothly transitioned to the 80386,
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
446 the RISC proponents were sure that better technology would eventually
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
447 prevail over market forces. The 386 was an extension of the 8086 which was
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
448 an extension of the 8080 which was an extension of the 8008. And the 386 wasn't
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
449 just similar to previous designs to ease porting, it actually implemented a
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
450 compatability mode to fully emulate the previous chip and run its software
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
451 unmodified! Surely this long chain of backwards compatability that had
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
452 accumulated customers for 20 years until it snowballed into market dominance
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
453 had to collapse from accumulated complexity at some point?</p>
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Rob Landley <rob@landley.net>
parents: 1595
diff changeset
454
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
455 <p>Next Intel came out with the 486, which introduced
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
456 CPU cache, allowing for "clock doubling" and "clock tripling" to run the
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
457 processor faster than the rest of the motherboard and execute loops of code
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
458 in cache while the slower main memory delivered the next part of the program
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
459 and stored the cached results of earlier computations. But the RISC proponents
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
460 saw this as merely buying time, sure that RISC would still win the day.</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
461
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
462 <p>Then Intel introduced the Pentium, which translated CISC instructions
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
463 into RISC internally. It could run as fast as RISC designs (executing two
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
464 instructions per clock cycle) while remaining compatible with existing
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
465 software.</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
466
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
467 <b>Mobile processors</b>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
468
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
469 <p>Intel did hit a bit of a wall at 1 gigahertz, and produced
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
470 a horrible RISC-like design (itanium) as its planned 64 bit transition,
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
471 but AMD filled the gap with other x86-compatible designs and a sane
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
472 64 bit extension of the x86 architecture (x86-64), and Intel's customers forced
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
473 it to adopt AMD's 64-bit design.</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
474
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
475 <p>Intel and AMD competed on two metrics: absolute performance, and the
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
476 price to performance ratio. They tried to produce the fastest chips, and
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
477 the fastest chip for the money.</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
478
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
479 <p>But in the late 90's laptop systems became a viable PC option, and
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
480 in 2005 laptops outsold desktops. These systems are battery powered, and
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
481 care about another metric: power consumption to performance ratio. The
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
482 best performance for the battery life. In 2000 a startup called Transmeta
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
483 (most widely known for employing Linus Torvalds in his first job out of
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
484 college) proved that a processor consuming just 1 watt could provide
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
485 reasonable performance. (Meanwhile Intel's itanium and Pentium 4 processors
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
486 consumed around 90 watts, enough power to fry an egg on the heat sink.)</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
487
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
488 <p>The processor with the best power consumption to performance ratio was
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
489 ARM, which came to dominate the cell phone and handheld systems. When those
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
490 coverged into smartphones, arm retained its dominant position.</p>
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
diff changeset
491
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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492 <p>Recently introduced processor designs attempted to compete with Arm, not
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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493 Intel. Coldfire was a stripped down version of m68k, and new designs include
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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494 blackfin, hexagon, tile, and so on. So far, these are doing as well against
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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495 arm as the RISC gold rush did against x86.<p>
1595
2ae38e4a36db Half-finished fluffing out of the architectures page.
Rob Landley <rob@landley.net>
parents: 1341
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496
2ae38e4a36db Half-finished fluffing out of the architectures page.
Rob Landley <rob@landley.net>
parents: 1341
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497
1600
e50c2b9588b8 Fluff out the architectures page.
Rob Landley <rob@landley.net>
parents: 1595
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498
881
0da87d1ef528 Update the web page. Put the left-side nav bar back, move about page to "about.html" and make news.html the default index. Add architectures page. Note that IRC discussion is now on #edev.
Rob Landley <rob@landley.net>
parents:
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499
0da87d1ef528 Update the web page. Put the left-side nav bar back, move about page to "about.html" and make news.html the default index. Add architectures page. Note that IRC discussion is now on #edev.
Rob Landley <rob@landley.net>
parents:
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500 <!--#include file="footer.html" -->