Mercurial > hg > toybox
comparison www/design.html @ 117:07d8795fc19c
Link to ars technica paedia broke because ars is now using Windows 2003 on
its' webserver and can't competently show "index.html" for a directory. Wheee.
| author | Rob Landley <rob@landley.net> |
|---|---|
| date | Thu, 17 May 2007 02:38:17 -0400 |
| parents | ce6956dfc0cf |
| children | 1e8f4b05cb65 |
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| 116:a0678c2ae9b8 | 117:07d8795fc19c |
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| 53 plus this | 53 plus this |
| 54 <a href=http://arstechnica.com/articles/paedia/cpu/caching.ars/1>article on | 54 <a href=http://arstechnica.com/articles/paedia/cpu/caching.ars/1>article on |
| 55 cacheing</a>, and this one on | 55 cacheing</a>, and this one on |
| 56 <a href=http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars>bandwidth | 56 <a href=http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars>bandwidth |
| 57 and latency</a>. | 57 and latency</a>. |
| 58 And there's <a href=http://arstechnica.com/paedia/>more where that came from</a>.) | 58 And there's <a href=http://arstechnica.com/paedia/index.html>more where that came from</a>.) |
| 59 Running out of L1 cache can execute one instruction per clock cycle, going | 59 Running out of L1 cache can execute one instruction per clock cycle, going |
| 60 to L2 cache costs a dozen or so clock cycles, and waiting for a worst case dram | 60 to L2 cache costs a dozen or so clock cycles, and waiting for a worst case dram |
| 61 fetch (round trip latency with a bank switch) can cost thousands of | 61 fetch (round trip latency with a bank switch) can cost thousands of |
| 62 clock cycles. (Historically, this disparity has gotten worse with time, | 62 clock cycles. (Historically, this disparity has gotten worse with time, |
| 63 just like the speed hit for swapping to disk. These days, a _big_ L1 cache | 63 just like the speed hit for swapping to disk. These days, a _big_ L1 cache |