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comparison sources/patches/linux-revertppcserial.patch @ 951:e6fd6f4fe67d

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Improved zilog serial fix from the ppc guys.
author Rob Landley <rob@landley.net>
date Thu, 14 Jan 2010 23:45:14 -0600
parents 4e798d7aa5f9
children
comparison
equal deleted inserted replaced
950:a43d74908821 951:e6fd6f4fe67d
1 diff -ru linux/drivers/serial/serial_core.c linux2/drivers/serial/serial_core.c 1 It seems that in qemu, we can see an interrupt in R3 despite the
2 --- linux/drivers/serial/serial_core.c 2009-12-02 21:51:21.000000000 -0600 2 fact that it's masked in W1. The chip doesn't actually issue an
3 +++ linux2/drivers/serial/serial_core.c 2009-12-08 06:17:06.000000000 -0600 3 interrupt, but we can "see" it when taking an interrupt for the
4 @@ -113,7 +113,7 @@ 4 other channel. This may be a qemu bug ... or not, so let's be
5 static void uart_tasklet_action(unsigned long data) 5 safe and avoid calling into the UART layer when that happens which
6 { 6 woulc cause a crash.
7 struct uart_state *state = (struct uart_state *)data; 7
8 - tty_wakeup(state->port.tty); 8 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 + if (state->port.tty) tty_wakeup(state->port.tty); 9 ---
10 } 10
11 David: This would affect sunzilog as well I believe. I'm not sure
12 if it's a bug in qemu emulation of the ESCC or if a real ESCC can
13 show it so I decided to be safe :-) The ESCC doc I have doesn't
14 appear to specify whether the interrupt status bits in R3 are
15 prior or post masking by W1. I can reproduce that by having the
16 kernel low level "udbg" debug console on channel B and the main
17 console on channel A (which is itself an uncommon setup).
18
19 diff --git a/drivers/serial/pmac_zilog.c b/drivers/serial/pmac_zilog.c
20 index 0700cd1..683e66f 100644
21 --- a/drivers/serial/pmac_zilog.c
22 +++ b/drivers/serial/pmac_zilog.c
23 @@ -411,6 +411,17 @@ static void pmz_transmit_chars(struct uart_pmac_port *uap)
24 goto ack_tx_int;
25 }
11 26
12 static inline void 27 + /* Under some circumstances, we see interrupts reported for
28 + * a closed channel. The interrupt mask in R1 is clear, but
29 + * R3 still signals the interrupts and we see them when taking
30 + * an interrupt for the other channel (this could be a qemu
31 + * bug but since the ESCC doc doesn't specify precsiely whether
32 + * R3 interrup status bits are masked by R1 interrupt enable
33 + * bits, better safe than sorry). --BenH.
34 + */
35 + if (!ZS_IS_OPEN(uap))
36 + goto ack_tx_int;
37 +
38 if (uap->port.x_char) {
39 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
40 write_zsdata(uap, uap->port.x_char);